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Contributor
Contributor
244 Views
Registered: ‎11-23-2018

[DRC PLIDC-4] IDELAYCTRL IODELAYs with conflicting groups for same bank: Found IODELAY cells with different IODELAY group constraints for same I/O bank 35.

In our design we are using two idelaye2 instance. I have a problem in MIG interface idelay control.

The design got failed in the write bitstream design. I followed the below thread to solve issue. But it didn't work.

Link : https://forums.xilinx.com/t5/Implementation/DRC-ERRORS-DRC-PLIDC-4-IDELAYCTRL-IODELAYs-with-Conflicting/td-p/877711

i have attached the dcp file in each stage.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: [DRC PLIDC-4] IDELAYCTRL IODELAYs with conflicting groups for same bank: Found IODELAY cells with different IODELAY group constraints for same I/O bank 35.

Do you have several MIG IPs in your design? Did you instantiate IODELAY outside MIG IP?

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Contributor
Contributor
182 Views
Registered: ‎11-23-2018

回复: [DRC PLIDC-4] IDELAYCTRL IODELAYs with conflicting groups for same bank: Found IODELAY cells with different IODELAY group constraints for same I/O bank 35.

No. i have single MIG IP in the design . Another module has idelaye2 instance with idelayctrl in the same design. i'm receving the HDMI input from the bank 34 subsequemtly bank 35 has MIG IP.

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