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Visitor
Visitor
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Registered: ‎02-02-2019

DRC Rule on DDR memory Interface Signals

 

Hi ,

I wanted to probe ddr_we_n for exampel on ILA. But DRC resulted in below failure. Does it affect DDR timing if this signal has more loads? Why this DRC rule?

Thanks,

Raghav

 

ERROR: [DRC REQP-127] obuf_loaded: OBUF chipset/chipset_impl/mc_top/u_mig_7series_axi4/u_mig_7series_axi4_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_we_n_obuf pin O drives one or more invalid loads. The loads are: chipset/chipset_impl/mc_top/debug_hawk_mc/inst/ila_core_inst/shifted_data_in_reg[7][772]_srl8, and chipset/chipset_impl/mc_top/debug_hawk_mc/inst/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[41].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg[0]

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Explorer
Explorer
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Registered: ‎06-20-2012

Re: DRC Rule on DDR memory Interface Signals

It seems to me that you are trying to read the output pin of an output buffer connected outside the FPGA fabric.

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