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Adventurer
Adventurer
8,058 Views
Registered: ‎10-06-2015

DRC error Conflicting Vcc voltages

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Hi,

 

During Implementation stage of QDR controller, I get the following error:

 

  • [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 33. For example, the following two ports in this bank have conflicting VCCOs: qdriip_k_p (DIFF_HSTL_II, requiring VCCO=1.500) and sys_rst (LVCMOS18, requiring VCCO=1.800)

I have given both sys_rst and qdriip_k_p signals to the pins mentioned in the device reference manual.

The solution to a similar problem had been given in http://www.xilinx.com/support/answers/64450.html. According to this, the DIFF_TERM property had to be set to FALSE. However, the property is FALSE by default for both the above mentioned signals. How do I resolve this issue?

 

Thanks.

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Xilinx Employee
Xilinx Employee
14,645 Views
Registered: ‎07-11-2011

@shashank0694

 

Change the IOstandard of your reset pin located at AA8 to HSTL_I or LVCMOS so that you can get rid of the DRC. As per the scheamtic this should work fine.

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Xilinx Employee
Xilinx Employee
8,053 Views
Registered: ‎07-11-2011

@shashank0694

 

You have to place the sys_rst such that its IOstandard does not conflict with existing pins IOstandards or chage the sys_rst IOstanard.

Please refer UG471 "Rules for Combining I/O Standards in the Same Bank" for more details

 

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

Hope this helps

 

-Vanitha

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Adventurer
Adventurer
8,041 Views
Registered: ‎10-06-2015

@vsrunga

 

I did refer to UG471. My main concern here is that the pins I have given in the constraints are the ones mentioned in the device reference manual. If the iostandards are incompatible then does it mean that the pins given in the manual are wrong?

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

@shashank0694

 

Pins may not be wrong, but they might have set a difefrent IOstandard in their project. and taken care of the IOlevels or bypassed the error by other means 

Do you have Digilent project with the same pinout and schematic?

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Adventurer
Adventurer
8,030 Views
Registered: ‎10-06-2015

I do not have a Digilent project with the same pin out specifications. 

Is it possible to use the same pin but use a different IO standard other than the one mentioned? 

If not, then shoud I use a different bank altogether?

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

@shashank0694

 

Do you have the board schematic, can you upload?

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Adventurer
Adventurer
8,018 Views
Registered: ‎10-06-2015

@vsrunga

 

PFA.

 

 

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Xilinx Employee
Xilinx Employee
14,646 Views
Registered: ‎07-11-2011

@shashank0694

 

Change the IOstandard of your reset pin located at AA8 to HSTL_I or LVCMOS so that you can get rid of the DRC. As per the scheamtic this should work fine.

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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Explorer
Explorer
897 Views
Registered: ‎10-16-2018

Hi @vsrunga ,

I got the same error but it is related to "sys_clock" port rather than "reset" port. What I have to do in order to solve this error ?

Note : I am using ARTY 7

"[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_sdram_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and sys_clock (LVCMOS33, requiring VCCO=3.300)"

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