11-11-2018 02:39 AM - last edited on 11-12-2018 12:36 AM by florentw
Although I find it a bit strange not to have a public bug tracking system for Vivado I will share my latest experience with an IP core here. Hope that helps or ends up in a solution/fix:
Using a Artix-7 board (Arty-A7) for smaller experiments I start to set up a MicroBlaze based design with DDR3 memory. After being done with that I make myself familiar with the petalinux flow.
The first improvement that I would do was to have the die-temperature from the XADC. I found the information that I have reconfigure the MIG to do not have its internal instance of the XADC and having the device_temp_i input feeded from the new dedicated XADC-Wizard instance. But when doing this simple change I ran into trouble. I figured out that the step of re configuring the MIG is the source of the problem. I don't do anything than set "XADC Intantiation" from Enabled to Disabled. What happens then is first: The summary in the Memory Interface Generator shows wrong information (Its independent from XADC changes. By the way if I change the period the clock value the display here is correct):
/* Controller 0 */
Controller Options :
Memory : DDR3_SDRAM
Interface : AXI
Design Clock Frequency : 3000 ps ( 0.00 MHz)
Phy to Controller Clock Ratio : 4:1
The line "Design Clock Frequency" do not showing the right frequency of 333.33 MHz). ok, that's a minor matter.
After finishing that dialog and pres "generate" a message comes up:
[Vivado 12-3563] The Nested sub-design '/home/alex/vivado/arty-based-projects/arty_base/arty_base.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1.xci' can only be generated by its parent sub-design.
This can be solved by a frequently useful and therefore frequently used manual "Reset Output Products" and "Generating Output Products".
But the following implementations fails with on the DRC:
[DRC PDRC-29] MMCM_adv_ClkFrequency_clkin1: The calculated frequency value, 833.333 MHz, of the CLKIN1_PERIOD attribute on the MMCME2_ADV site MMCME2_ADV_X1Y0 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) is outside the allowed range (10.000 - 800.000 MHz). Please change the CLKIN1_PERIOD attribute value in order to be within the allowed range for this device.
[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 6666.667 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y0 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (1.200000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.
My solution was to copy the board-files for the arty-a7 board and set the element <XADC_En> from Enabled to Disabled in the file mig.prj. Creating a new block-design with those board-file than get good results due to the fact that I must no longer touch the Re-customize IP process for the MIG. Even if I change nothing in the MIG the above failure occurs.
Hope that helps an this is the right place to display that.
Using Vivado 2018.2 on Linux
11-12-2018 12:04 PM - edited 11-12-2018 12:09 PM
I have not seen this behavior before with re-customization of 7-series MIG. I was going to suggest modifying the PRJ that is delivered with the Arty-A7 board as it's just a single parameter from True to False.
Let me see if I can reproduce the issue in Vivado 2018.2 that you first described. Specifically which Art-A7 board are you using? I see Arty A7-100/Arty A7-35/Arty A7-25 and just Arty.
11-13-2018 12:20 AM
wow, quick response! I'm impressed.
I use an Arty-A7-35T board, nice little toy. In the meantime I found a negligence on my side that I do not want to conceal: I have installed Vivado 18.2 on Ubuntu 18.04. I'm not sure if Vivado displayed this to me when installing (I know in the past I saw such messages when installing but I think this was with ISE). I noticed it during the installation of petalinux. The petalinux environment fails totally on Ubutnu 18.04. Then I found then the information that 18.04 is not supported. I set up a virtual machine with 16.04 and it works there. I will try myself to reproduce the effect with the MIG on Ubuntu 16.04 after installing Vivado in the virtual machine.
11-13-2018 08:53 AM
I know that UG973 says Vivado 2018.2 does not support Ubuntu 18.04 (2018.3 will support it.) Also looking at UG1144 PetaLinux also does not support Ubuntu 18.04.
11-14-2018 06:53 AM
Embarrassingly the information of supported versions of different Distributions is just in the first screen when installing Vivado. I must have overlooked that.
I saw it when installing Vivado in the virtual machine running 16.04 and I made the test.
The exact same behavior in the DRC occurs under Ubuntu 16.04.
So I'm now sure that this is a bug in 2018.2.
11-15-2018 09:34 AM
After Re-Customizing the MIG IP (turning off the XADC) I see the following pop-up. You should hit "skip" at this time. This pop-up should not be occurring.
After hitting "skip" I then pulled the device_temp_i port external, re-validate the BD, and then click on "Generate Block Design." This should allow you to get around your issue.
I will need to file a Change Request to stop the MIG Pop-Up from occurring after re-customizing.
11-15-2018 10:54 AM
I filed a Change Request to resolve the pop-up window.