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chlwogns414
Participant
Participant
517 Views
Registered: ‎12-06-2018

Data conversion using MIG

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I am trying to control DDR memory by MIG.

The final Goal is that FPGA get 16 bit ADC data and write data to app_wdf_data(128 bit).

I was wondering how to make data. I thought one idea like below.

1. write

write data.png

 

 

After writing data, I have to read data and send it to MCU using EIM.

When I read data from DDR is it possible to make data like below?

2. read

read data.png

 

Timing chart seems to be poor. I want to know that it is possible to make interface like picture.

If I can't, could you share Idea to make interface to achieve my Goal?

 

Thank You.

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kren
Moderator
Moderator
487 Views
Registered: ‎08-21-2007

I suggest you create a user FIFO when comunicating with the MIG user interface. You can refer to pg150 (https://china.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf) for details on the user interface timing.

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kren
Moderator
Moderator
488 Views
Registered: ‎08-21-2007

I suggest you create a user FIFO when comunicating with the MIG user interface. You can refer to pg150 (https://china.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf) for details on the user interface timing.

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kshimizu
Xilinx Employee
Xilinx Employee
428 Views
Registered: ‎03-04-2018

Hello @chlwogns414 ,

 

What you mention is one of way.  Please inputs your data to user_interface(MIG) as shown in Figure4-2, -3 and -4 in PG150.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

An example simuation is also possible, so please try it to ensure your idea.

 

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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f1-1.PNG
f4-2.PNG