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kimsclub007
Observer
Observer
7,172 Views
Registered: ‎06-03-2014

Design failed to meet timing requirement. (MIG7 PHY)

Hello,

I tried to generate bitstream for VC709 board.
The design includes 2channel of DDR3 interface. Each channel is connected to each sodimm.
I connected MIG7 phy with customized DDR3 controller. And I got XDC of vc709_mig_bank_a_b example.
Bitstream generation was done. But there are timing slacks in the PHY. Could you let me know how to resolve this problem?


Thanks.

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vsrunga
Xilinx Employee
Xilinx Employee
7,155 Views
Registered: ‎07-11-2011

Hi,

 

DId you see the timing errors with example design and just replacing the controller you met with errors?

As you used you are using your own DDR3 controller what exactly is your flow ?

can you provide a block diagram representation of clocking, phy and controller?

 

 

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