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Visitor
Visitor
4,684 Views
Registered: ‎01-17-2008

Design w/ multiple MIGs

I am working in Vivado 2015.4 with several variations of a design that uses four MIGs to control 4 separate banks of DDR3 memory.  I note that in the designs I have previously produced, in the Configuration Files folder in the Hierarchy tab, I would see two files named "mig_a.prj" and two named "mig_b.prj".  In my most recent project, however, I note 3 instances of mig_a.prj, and only one mig_b.

 

What is the purpose of these project files, and what differentiates a mig_a project from a mig_b project?  Can I expect one of the memory controllers to fail because it should be a "b", but has been designated as an "a"?

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Visitor
Visitor
4,680 Views
Registered: ‎01-17-2008

BTW - the MIG version for the above project is Ver. 2.4, rev.1

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Xilinx Employee
Xilinx Employee
4,655 Views
Registered: ‎08-01-2008

If the MIG in the BD is multi-controller then there will be more than one mig_#.prj file
check this ARs
http://www.xilinx.com/support/answers/58852.html
Thanks and Regards
Balkrishan
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