11-27-2014 12:37 AM
So i move to the next chunk of 256 commands. Here when i observed at the DDR side memory signals the address are going on correctly, but the data sent is missing first two 256bit data items. I am not able to find the reason behind it.
User interface information:
app_addr width 28 bit.
ddr_DQ data bus width 72 bit
interface clock 200MHZ
DDR3 frequency is 400MHZ
for every address i am sending 512 bits (BC8 burst length)
11-27-2014 12:46 AM
Is this seen in simulation or hardware.
Can you upload the captures showing the issue to look at it and give you suggestions.
11-27-2014 01:02 AM - edited 11-27-2014 01:15 AM
I donot think data will be missing but suspect it might not be properly aligned.
Please cross check your app_* interface signal timings againt the ones given in UG586 command, write and read interface timing diagrams and make sure that max delay between command and corresponding write is not more than 2 clocks
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Hope this helps
11-27-2014 05:37 AM
I am also attaching screen shots of how RAM address and data changing at starting each write cycle.
during start of write cycle the RAM enable signal is asserted but address pointer increment is not starting from zero
I am taking about the signals present in u_ui_top/ui_write_data/wdf_rdy_ns , wr_data and rd_addr_w.
11-27-2014 09:32 PM
What is your Vivado Version and which simualtor is this?
Are you using MIG generated memory model and supported simulators ?
Can you send us your ready to simulate design for investigation or vcd wavs form dumps with all the required signals?