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Contributor
Contributor
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Registered: ‎02-28-2018

Do the PS and PL of XC7Z045 devices share a single DDR3 port?

I know that PS and PL of XC7Z035 devices have their own DDR3 ports, but I can't find the description in UG585. Is the XC7Z045 device the same? and can you tell me which document it is described in? thanks!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-04-2018

Hello @daowen ,

 

From the UG585, page 294, there is no “notice” and “restriction” regarding XC7Z035 and XC7Z045 devices.  so, you can use the XC7Z045 like XC7Z035.

https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

 

I also check the DS191 to see the difference about Memory Interface, but I coul not find out.

https://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf

 

 

Best regards,

Kshimizu

Product Application Engineer Xilinx Technical Support

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Moderator
Moderator
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Registered: ‎08-21-2007

PS DDR3 interface is on the dedicated pins. You can find the detailed information in serction "DDR IOB Configuration" of ug585.

For PL DDR3, the interface is implemented on general IO with some pinout rules followed. You can find the rules in section "Bank and Pin Selection Guides for DDR3 Designs" of ug586.

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