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Visitor yang_hailei
Visitor
576 Views
Registered: ‎07-08-2018

ECCCADDR1 in DDRC Module

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I'm using DDR4 in my system, and need open ecc.

But I'm confused by a register named ECCCADDR1.

In this register the field name ecc_corr_col give a description. and I don't know what is the 'beat' , the number 0 and number 4 in description.

The ecc_corr_col should indicates the column number, and why the beat in this field??

If the ecc_corr_col stand for the column number and beat number, the 4(b'100) of beat should 3 bits width and column must 10 bits width.

The ecc_corr_col is 12 bits width.                       12  [11:0]   <  13 =  3 + 10 .

 

 

This is the register of ECCCADDR1

image.png

 

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Moderator
Moderator
545 Views
Registered: ‎11-28-2016

Re: ECCCADDR1 in DDRC Module

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Hello @yang_hailei,

This is due to the nature of the DDR4 burst length which is always 8 for this controller.  This means the command will be issued to a column address but 8 bursts of data will come from the memory, meaning 8 consecutive column addresses will be read. The least significant 4-bits of the column address will either be 0x8 or 0x0 for every command issued by the controller.  Now if you exclude bit 3 then bits 2-0 will tell you if the ECC error happened.  If bits 2:0 = 0x0 then the error was detected within the first 4 bursts (bust 0-3) of the access and if bits 2:0 = 0x4 then the error was detected within the last 4 bursts (burst 4-7).

4 Replies
Moderator
Moderator
546 Views
Registered: ‎11-28-2016

Re: ECCCADDR1 in DDRC Module

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Hello @yang_hailei,

This is due to the nature of the DDR4 burst length which is always 8 for this controller.  This means the command will be issued to a column address but 8 bursts of data will come from the memory, meaning 8 consecutive column addresses will be read. The least significant 4-bits of the column address will either be 0x8 or 0x0 for every command issued by the controller.  Now if you exclude bit 3 then bits 2-0 will tell you if the ECC error happened.  If bits 2:0 = 0x0 then the error was detected within the first 4 bursts (bust 0-3) of the access and if bits 2:0 = 0x4 then the error was detected within the last 4 bursts (burst 4-7).

Visitor yang_hailei
Visitor
528 Views
Registered: ‎07-08-2018

Re: ECCCADDR1 in DDRC Module

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Hi, ryana

Thanks your reply.

I think I know the meaning of the column address.

That is if I got a value 0x14 = 20 (0x10= 16 = 2 * 8 ,0x04 = b'100),  it indicates that the error in the third burst and in the 16th-20th column?

The value of the column will never be 0x01 0x02 0x03 0x05 0x06 0x07 ?

 

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Moderator
Moderator
506 Views
Registered: ‎11-28-2016

Re: ECCCADDR1 in DDRC Module

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Hello @yang_hailei,

If you got a value of 0x14 then the read was issue to column address 0x10 and the error was detected in burst 4-7, so the start was column 16 and the error was detected somewhere in column address 20-23.  The lowest nibble of this column register will only be 0x0, 0x4, 0x8, or 0xC.

Visitor yang_hailei
Visitor
483 Views
Registered: ‎07-08-2018

Re: ECCCADDR1 in DDRC Module

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Thank you!

I think I know how to calculate the column address.

 

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