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raghavs
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Registered: ‎02-02-2019

ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are

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Hi,
 
My Design was working fine with mig_7series (Without AXI).
Now, I needed mig_7series (with AXI) based memory controller.
I have attached mig_7series_axi4 configuration that was used to generate using MIG wizard.
 
I am using Vivado 2018.2. and Digilent genesys2 board.
I see below error during implementation. Can you please give me a hint to solve this?
 
 
ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are chipset/clk_mmcm/inst/mc_sys_clk
In above message, mc_sys_clk is connecte to both "sys_clk" and "ref_clk" at mig_7series_axi4 instance.
 
Thank you!,
Raghav
 
 
 
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kren
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Registered: ‎08-21-2007

There will not be any functional problem.

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yangc
Xilinx Employee
Xilinx Employee
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Registered: ‎02-27-2019

please refer to https://forums.xilinx.com/t5/Implementation/DRC-RTRES-1-Backbone-resources-1-net-s-have-CLOCK-DEDICATED/m-p/1042044 to have a try.

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raghavs
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Registered: ‎02-02-2019

Hi,

I set it to CLOCK_DEDICATED_ROUTE set to FALSE to avoid error, NOT sure if it creates any functional issues.

I will update here later.

Thanks,

Raghav

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kren
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432 Views
Registered: ‎08-21-2007

There will not be any functional problem.

-----------------------------------------------------Please don't forget to give kudos or accept as solution if information provided is helpful.---------------------------------------------------------------------

View solution in original post