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penn
Observer
Observer
10,639 Views
Registered: ‎04-02-2014

ERROR place:906 when I user MIG with the xilinx v5

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Hi,

 

I use the xilinx virtex-5 220T FPGA board and ISE14.5 at windows 7 to creat the ddr2 controller for my project. And the top-level block diagram is figure 9-6 of ug086.Without a PLL,so I use the IP core of PLL to creat 4 output clock as clk0,clk90,clkdiv0 and clk200.

 

The top module as follow:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ddrsdram is
  generic(
   BANK_WIDTH               : integer := 3; 
                              -- # of memory bank addr bits.
   CKE_WIDTH                : integer := 1; 
                              -- # of memory clock enable outputs.
   CLK_WIDTH                : integer := 2; 
                              -- # of clock outputs.
   COL_WIDTH                : integer := 10; 
                              -- # of memory column bits.
   CS_NUM                   : integer := 1; 
                              -- # of separate memory chip selects.
   CS_WIDTH                 : integer := 1; 
                              -- # of total memory chip selects.
   CS_BITS                  : integer := 0; 
                              -- set to log2(CS_NUM) (rounded up).
   DM_WIDTH                 : integer := 8; 
                              -- # of data mask bits.
   DQ_WIDTH                 : integer := 64; 
                              -- # of data width.
   DQ_PER_DQS               : integer := 8; 
                              -- # of DQ data bits per strobe.
   DQS_WIDTH                : integer := 8; 
                              -- # of DQS strobes.
   DQ_BITS                  : integer := 6; 
                              -- set to log2(DQS_WIDTH*DQ_PER_DQS).
   DQS_BITS                 : integer := 3; 
                              -- set to log2(DQS_WIDTH).
   ODT_WIDTH                : integer := 1; 
                              -- # of memory on-die term enables.
   ROW_WIDTH                : integer := 14; 
                              -- # of memory row and # of addr bits.
   ADDITIVE_LAT             : integer := 0; 
                              -- additive write latency.
   BURST_LEN                : integer := 4; 
                              -- burst length (in double words).
   BURST_TYPE               : integer := 0; 
                              -- burst type (=0 seq; =1 interleaved).
   CAS_LAT                  : integer := 4; 
                              -- CAS latency.
   ECC_ENABLE               : integer := 0; 
                              -- enable ECC (=1 enable).
   APPDATA_WIDTH            : integer := 128; 
                              -- # of usr read/write data bus bits.
   MULTI_BANK_EN            : integer := 1; 
                              -- Keeps multiple banks open. (= 1 enable).
   TWO_T_TIME_EN            : integer := 1; 
                              -- 2t timing for unbuffered dimms.
   ODT_TYPE                 : integer := 1; 
                              -- ODT (=0(none),=1(75),=2(150),=3(50)).
   REDUCE_DRV               : integer := 0; 
                              -- reduced strength mem I/O (=1 yes).
   REG_ENABLE               : integer := 0; 
                              -- registered addr/ctrl (=1 yes).
   TREFI_NS                 : integer := 7800; 
                              -- auto refresh interval (ns).
   TRAS                     : integer := 40000; 
                              -- active->precharge delay.
   TRCD                     : integer := 15000; 
                              -- active->read/write delay.
   TRFC                     : integer := 127500; 
                              -- refresh->refresh, refresh->active delay.
   TRP                      : integer := 15000; 
                              -- precharge->command delay.
   TRTP                     : integer := 7500; 
                              -- read->precharge delay.
   TWR                      : integer := 15000; 
                              -- used to determine write->precharge.
   TWTR                     : integer := 7500; 
                              -- write->read delay.
   HIGH_PERFORMANCE_MODE    : boolean := TRUE; 

   SIM_ONLY                 : integer := 0; 
                              -- = 1 to skip SDRAM power up delay.
   DEBUG_EN                 : integer := 0; 
                              -- Enable debug signals/controls.
                              -- When this parameter is changed from 0 to 1,
                              -- make sure to uncomment the coregen commands
                              -- in ise_flow.bat or create_ise.bat files in
                              -- par folder.
   CLK_PERIOD               : integer := 3750; 
                              -- Core/Memory clock period (in ps).
   RST_ACT_LOW              : integer := 1  
                              -- =1 for active low reset, =0 for active high.
   );
  port(
   ddr2_dq               : inout  std_logic_vector((DQ_WIDTH-1) downto 0);
   ddr2_a                : out   std_logic_vector((ROW_WIDTH-1) downto 0);
   ddr2_ba               : out   std_logic_vector((BANK_WIDTH-1) downto 0);
   ddr2_ras_n            : out   std_logic;
   ddr2_cas_n            : out   std_logic;
   ddr2_we_n             : out   std_logic;
   ddr2_cs_n             : out   std_logic_vector((CS_WIDTH-1) downto 0);
   ddr2_odt              : out   std_logic_vector((ODT_WIDTH-1) downto 0);
   ddr2_cke              : out   std_logic_vector((CKE_WIDTH-1) downto 0);
   ddr2_dm               : out   std_logic_vector((DM_WIDTH-1) downto 0);
	
   sys_rst_n             : in    std_logic;
	clk_in					 :	in		std_logic;		--input clock = 25M
	
   phy_init_done         : out   std_logic;
   error                 : out   std_logic;

   ddr2_dqs              : inout  std_logic_vector((DQS_WIDTH-1) downto 0);
   ddr2_dqs_n            : inout  std_logic_vector((DQS_WIDTH-1) downto 0);
   ddr2_ck               : out   std_logic_vector((CLK_WIDTH-1) downto 0);
   ddr2_ck_n             : out   std_logic_vector((CLK_WIDTH-1) downto 0)
   );
	
end ddrsdram;

architecture Behavioral of ddrsdram is
	signal ddr2_clk200		:		std_logic;
	signal ddr2_clk0		:		std_logic;
	signal ddr2_clk90		:		std_logic;
	signal ddr2_clkdiv0	:		std_logic;
	signal locked			:		std_logic;
	signal sys_res_n_t   :     std_logic;

component clk
		port(
			 CLKIN1_IN   : in    std_logic; 
          RST_IN      : in    std_logic; 
          CLKOUT0_OUT : out   std_logic; 
          CLKOUT1_OUT : out   std_logic; 
          CLKOUT2_OUT : out   std_logic; 
          CLKOUT3_OUT : out   std_logic; 
          LOCKED_OUT  : out   std_logic		
			);
end component;

component migtest
	generic(
			BANK_WIDTH               : integer; 
			CKE_WIDTH                : integer; 
			CLK_WIDTH                : integer; 
			COL_WIDTH                : integer; 
			CS_NUM                   : integer; 
			CS_WIDTH                 : integer; 
			CS_BITS                  : integer; 
			DM_WIDTH                 : integer; 
			DQ_WIDTH                 : integer; 

			DQ_PER_DQS               : integer; 
			DQS_WIDTH                : integer; 
			DQ_BITS                  : integer; 
			DQS_BITS                 : integer; 
			ODT_WIDTH                : integer; 
			ROW_WIDTH                : integer; 
			ADDITIVE_LAT             : integer; 
			BURST_LEN                : integer; 
			BURST_TYPE               : integer; 
			CAS_LAT                  : integer; 
			ECC_ENABLE               : integer; 
			APPDATA_WIDTH            : integer; 
			MULTI_BANK_EN            : integer; 
			TWO_T_TIME_EN            : integer; 
			ODT_TYPE                 : integer; 
			REDUCE_DRV               : integer; 
			REG_ENABLE               : integer; 
			TREFI_NS                 : integer; 
			TRAS                     : integer; 
			TRCD                     : integer; 
			TRFC                     : integer; 
			TRP                      : integer; 
			TRTP                     : integer; 
			TWR                      : integer; 
			TWTR                     : integer; 
			HIGH_PERFORMANCE_MODE    : boolean; 
			SIM_ONLY                 : integer; 
			DEBUG_EN                 : integer; 
			CLK_PERIOD               : integer; 
			RST_ACT_LOW              : integer
			);
		port(
			ddr2_dq               : inout  std_logic_vector((DQ_WIDTH-1) downto 0);
			ddr2_a                : out   std_logic_vector((ROW_WIDTH-1) downto 0);
			ddr2_ba               : out   std_logic_vector((BANK_WIDTH-1) downto 0);
			ddr2_ras_n            : out   std_logic;
			ddr2_cas_n            : out   std_logic;
			ddr2_we_n             : out   std_logic;
			ddr2_cs_n             : out   std_logic_vector((CS_WIDTH-1) downto 0);
			ddr2_odt              : out   std_logic_vector((ODT_WIDTH-1) downto 0);
			ddr2_cke              : out   std_logic_vector((CKE_WIDTH-1) downto 0);
			ddr2_dm               : out   std_logic_vector((DM_WIDTH-1) downto 0);
			sys_rst_n             : in    std_logic;
			phy_init_done         : out   std_logic;
			error                 : out   std_logic;
			locked                : in    std_logic;
			clk0                  : in    std_logic;
			clk90                 : in    std_logic;
			clkdiv0               : in    std_logic;
			clk200                : in    std_logic;
			ddr2_dqs              : inout  std_logic_vector((DQS_WIDTH-1) downto 0);
			ddr2_dqs_n            : inout  std_logic_vector((DQS_WIDTH-1) downto 0);
			ddr2_ck               : out   std_logic_vector((CLK_WIDTH-1) downto 0);
			ddr2_ck_n             : out   std_logic_vector((CLK_WIDTH-1) downto 0)
			);
end component;

begin
	u_clk:clk port map
	(
			 CLKIN1_IN   				=>		clk_in, 
          RST_IN      				=>		sys_rst_n,
          CLKOUT0_OUT				=>    ddr2_clk0, 
          CLKOUT1_OUT				=>		ddr2_clk90, 
          CLKOUT2_OUT				=>		ddr2_clkdiv0, 
          CLKOUT3_OUT				=>		ddr2_clk200, 
          LOCKED_OUT					=>    locked		
	);
	
	u_ddr:migtest generic map
	(
			BANK_WIDTH     => BANK_WIDTH, 
			CKE_WIDTH 		=> CKE_WIDTH,
			CLK_WIDTH      => CLK_WIDTH, 
			COL_WIDTH      => COL_WIDTH, 
			CS_NUM			=> CS_NUM,
			CS_WIDTH			=> CS_WIDTH, 
			CS_BITS        => CS_BITS,
			DM_WIDTH       => DM_WIDTH, 
			DQ_WIDTH       => DQ_WIDTH, 

			DQ_PER_DQS              => DQ_PER_DQS, 
			DQS_WIDTH               => DQS_WIDTH, 
			DQ_BITS                 => DQ_BITS, 
			DQS_BITS                => DQS_BITS, 
			ODT_WIDTH               => ODT_WIDTH,
			ROW_WIDTH               => ROW_WIDTH, 
			ADDITIVE_LAT            => ADDITIVE_LAT,
			BURST_LEN               => BURST_LEN, 
			BURST_TYPE              => BURST_TYPE, 
			CAS_LAT                 => CAS_LAT,
			ECC_ENABLE              => ECC_ENABLE, 
			APPDATA_WIDTH           => APPDATA_WIDTH,
			MULTI_BANK_EN           => MULTI_BANK_EN,
			TWO_T_TIME_EN           => TWO_T_TIME_EN, 
			ODT_TYPE                => ODT_TYPE, 
			REDUCE_DRV              => REDUCE_DRV, 
			REG_ENABLE              => REG_ENABLE, 
			TREFI_NS                => TREFI_NS,
			TRAS                    => TRAS, 
			TRCD                   => TRCD, 
			TRFC                    => TRFC, 
			TRP                     => TRP, 
			TRTP                    => TRTP, 
			TWR                     => TWR, 
			TWTR                    => TWTR, 
			HIGH_PERFORMANCE_MODE   => HIGH_PERFORMANCE_MODE, 
			SIM_ONLY       => SIM_ONLY, 
			DEBUG_EN       => DEBUG_EN, 
			CLK_PERIOD     => CLK_PERIOD, 
			RST_ACT_LOW    => RST_ACT_LOW
	)
	port map
	(
			ddr2_dq            	=> ddr2_dq,
			ddr2_a                	=> ddr2_a,
			ddr2_ba               	=> ddr2_ba,
			ddr2_ras_n            	=> ddr2_ras_n,
			ddr2_cas_n            	=> ddr2_cas_n,
			ddr2_we_n             	=> ddr2_we_n,
			ddr2_cs_n             	=> ddr2_cs_n,
			ddr2_odt              	=> ddr2_odt,
			ddr2_cke              	=> ddr2_cke,
			ddr2_dm               	=> ddr2_dm,
			
			sys_rst_n             	=> sys_rst_n,
			phy_init_done         	=> phy_init_done,
			error                 	=> error,
			locked                	=> locked,
			clk0                  	=> ddr2_clk0,
			clk90                 	=> ddr2_clk90,
			clkdiv0               	=> ddr2_clkdiv0,
			clk200                	=> ddr2_clk200,
			ddr2_dqs              	=> ddr2_dqs,
			ddr2_dqs_n            	=> ddr2_dqs_n,
			ddr2_ck               	=> ddr2_ck,
			ddr2_ck_n             	=> ddr2_ck_n
	);

end Behavioral;

By the way ,the clk_in is 25M.

 

But now when I map it in Implement Design some wrong have happened.

 

ERROR:Place:906 - Components driven by IO clock net
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> can't be
   placed and routed because location constraints are causing the clock region
   rules to be violated. IO Clock net
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> is being
   driven by BUFIO
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bu
   fio_dqs> locked to site "BUFIO_X2Y12" Because of this location contraint,
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> can only
   drive clock region "CLOCKREGION_X1Y3". The following components driven by
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>> have been
   locked to sites outside of these clock regions:
   u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<7> (Locked Site:
   ILOGIC_X2Y100 CLOCKREGION_X1Y2)
   Please evaluate the location constraints of both the BUFIO and the components
   driven by <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>>
   to ensure that they follow the clock region rules of the architecture. For
   more information on the clock region rules, please refer to the architecture
   user's guide. To debug your design with partially routed design, please allow
   mapper/placer to finish the execution (by setting environment variable
   XIL_PAR_DEBUG_IOCLKPLACER to 1).
ERROR:Place:906 - Components driven by IO clock net
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>> can't be
   placed and routed because location constraints are causing the clock region
   rules to be violated. IO Clock net
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>> is being
   driven by BUFIO
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bu
   fio_dqs> locked to site "BUFIO_X2Y11" Because of this location contraint,
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>> can only
   drive clock region "CLOCKREGION_X1Y2". The following components driven by
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>> have been
   locked to sites outside of these clock regions:
   u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<4> (Locked Site:
   ILOGIC_X2Y140 CLOCKREGION_X1Y3)
   Please evaluate the location constraints of both the BUFIO and the components
   driven by <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>>
   to ensure that they follow the clock region rules of the architecture. For
   more information on the clock region rules, please refer to the architecture
   user's guide. To debug your design with partially routed design, please allow
   mapper/placer to finish the execution (by setting environment variable
   XIL_PAR_DEBUG_IOCLKPLACER to 1).
ERROR:Place:906 - Components driven by IO clock net
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>> can't be
   placed and routed because location constraints are causing the clock region
   rules to be violated. IO Clock net
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>> is being
   driven by BUFIO
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bu
   fio_dqs> locked to site "BUFIO_X2Y10" Because of this location contraint,
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>> can only
   drive clock region "CLOCKREGION_X1Y2". The following components driven by
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>> have been
   locked to sites outside of these clock regions:
   u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> (Locked Site:
   ILOGIC_X2Y138 CLOCKREGION_X1Y3)
   Please evaluate the location constraints of both the BUFIO and the components
   driven by <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>>
   to ensure that they follow the clock region rules of the architecture. For
   more information on the clock region rules, please refer to the architecture
   user's guide. To debug your design with partially routed design, please allow
   mapper/placer to finish the execution (by setting environment variable
   XIL_PAR_DEBUG_IOCLKPLACER to 1).
ERROR:Place:906 - Components driven by IO clock net
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>> can't be
   placed and routed because location constraints are causing the clock region
   rules to be violated. IO Clock net
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>> is being
   driven by BUFIO
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bu
   fio_dqs> locked to site "BUFIO_X2Y14" Because of this location contraint,
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>> can only
   drive clock region "CLOCKREGION_X1Y3". The following components driven by
   <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>> have been
   locked to sites outside of these clock regions:
   u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<6> (Locked Site:
   ILOGIC_X2Y102 CLOCKREGION_X1Y2)
   Please evaluate the location constraints of both the BUFIO and the components
   driven by <u_ddr/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>>
   to ensure that they follow the clock region rules of the architecture. For
   more information on the clock region rules, please refer to the architecture
   user's guide. To debug your design with partially routed design, please allow
   mapper/placer to finish the execution (by setting environment variable
   XIL_PAR_DEBUG_IOCLKPLACER to 1).
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Could someone tell me what cause these errors and how to solve it?

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1 Solution

Accepted Solutions
criley
Xilinx Employee
Xilinx Employee
17,326 Views
Registered: ‎08-16-2007

Check your pinout for any violations. I'm guessing you don't have all your data signals placed in the same bank as your DQS. The DQS passes through a BUFIO to delay the corresponding DQ bits but they need to be in the same bank so the BUFIO can drive them.

 

Also, check which pins your input system clock is coming in on and where you have the BUFIO loc'ed down. You may need to change the location constraint as suggested in the error message.

View solution in original post

7 Replies
criley
Xilinx Employee
Xilinx Employee
17,327 Views
Registered: ‎08-16-2007

Check your pinout for any violations. I'm guessing you don't have all your data signals placed in the same bank as your DQS. The DQS passes through a BUFIO to delay the corresponding DQ bits but they need to be in the same bank so the BUFIO can drive them.

 

Also, check which pins your input system clock is coming in on and where you have the BUFIO loc'ed down. You may need to change the location constraint as suggested in the error message.

View solution in original post

penn
Observer
Observer
10,603 Views
Registered: ‎04-02-2014

Hi,

 

Thanks for your reply.

 

I found A mistake what I connected the dqs6 to BANK 17,

 

After fixed the error,I checked my pinout and I have all  my signals placed in the same bank as my DQS.

 

The Xilinx device is XC5VLX220-1760.

 

In BANK 12,I place the DQ0~DQ7, DM0,DQS0,DQS0_N, 

                                     DQ8~DQ15, DM1,DQS1,DQS1_N

                                     DQ16~DQ23, DM2,DQS2,DQS2_N

 

In BANK 14,I place the DQ24~DQ31,DM3,DQS3,DQS3_N, 

                                     DQ48~DQ55,DM1,DQS6,DQS6_N

                                     DQ56~DQ63,DM2,DQS7,DQS7_N

 

In BANK 18,I place the DQ32~DQ39,DM0,DQS4,DQS4_N, 

                                     DQ40~DQ47,DM1,DQS5,DQS5_N

 

In BANK 16,I place the address0~address13,odt,ck,cke and other control signals. 

 

In additional,the sys_clk pin been connected to K15(IO_L0P_CC_GC_3).

 

However,the error persists.

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criley
Xilinx Employee
Xilinx Employee
10,597 Views
Registered: ‎08-16-2007

What about the BUFIO location? Is it LOC'ed to the correct place?

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penn
Observer
Observer
10,593 Views
Registered: ‎04-02-2014

Thanks.

 

I have found the problem.

 

But when I Place & Route, another a error happened as follow.

 

sys_clk.png

 

I have add "NET "sys_clk_i" CLOCK_DEDICATED_ROUTE = FALSE;", but in .unroutes file the "sys_clk_i" still not be routeds.

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criley
Xilinx Employee
Xilinx Employee
10,590 Views
Registered: ‎08-16-2007

What type of IO are you bringing sys_clk in on?

Are you using a differential or single ended input clock?

Why do you have CLOCK_DEDICATED_ROUTE constraint set for sys_clk?

 

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penn
Observer
Observer
10,587 Views
Registered: ‎04-02-2014

I am using single ended input clock.

 

The sys_clk should have connect to the GC pin such as the IO_L0P_CC_GC_3(K15), but in my board,the sys_clk been connected to the IO_L11P_CC_15(K40).

 

According the warnings of ISE,I added a CLOCK_DEDICATED_ROUTE constraint for my sys_clk.

 

Best Regards.

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criley
Xilinx Employee
Xilinx Employee
10,582 Views
Registered: ‎08-16-2007

Can you open a new thread on this new error in the Design Tools=>Implementation fprum?

I thin this warrants a new thread and you'll probably get a faster answer from implementation experts since this problem doesn't seem specific to MIG.

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