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281 Views
Registered: ‎10-07-2020

Example design of DDR4 IP has timing failures on Kintex UltraScale Device

Hi,

I have generated the example device by right-clicking on ddr4_0.xci. Then I synthesized the design and clicked on report timing summary. Unfortunately, Hold Slack (WHS and THS) is failing for the example design. I am using Vivado 2019.2 and I implemented the design on Kintex xcku060-ffva1517-1-c (active) device. I have attached all the screenshots of how I configure the DDR4 IP, timing summary, failing paths and timing report

Thanks,

Koshila

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280 Views
Registered: ‎10-07-2020

timing.rpx file is attached here

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-04-2018

Hello @koshilagimhanis ,

 

I could not find out the same error you pointed out.  I created an example design based on your settings.  Could you please try to create an example design only.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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