Example design of Kintex UltraScale DDR4 memory controller timing failure

[sasindugeemal]

I am trying to run DDR4 example design on Xilinx Kintex Ultrascale XCKU060-1FFVA1517C device with a 8 GB SODIMM (from the existing device list). When I synthesis the example design Total Hold Stack (THS) fails. I need to figure out the reason behind it. I am driving the clock at 351 MHz. I have attached the screenshots of the error and the configurations.

[calebd]

Hello @sasindugeemal 

I ran the example design targetting your part, and do not run into any timing issues.  Can you provide your constraints in this design?  It seems like it may be possible that there is something conflicting between a constraint in your design.

Otherwise, can you try starting from scratch and creating the MIG example design by right-clicking on the IP .xci, and selecting "Open IP Example Design..."

[sasindugeemal]

Hi @calebd ,

I tried the example design too. To figure out timing, after synthesis step, I clicked on report timing summary and ran it for default configuration and end up having THS violation. I am using vivado 2019.2

Thanks,

Sasindu 

[sasindugeemal]

I am attaching my constraints file below.

Thanks,

Sasindu

[kshimizu]

Hello @sasindugeemal ,

I think it is the same question as below.  I could not find out the same error with same settings.

https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/Example-design-of-DDR4-IP-has-timing-failures-on-Kintex/td-p/1159504

Best regards,

Kshimizu

Product Application Engineer Xilinx Technical Support

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