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tte_yoshida
Contributor
Contributor
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Registered: ‎05-28-2015

Exclusive memory access from APU and RPU

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Hello,

We are considering developing an MPSoC board.
I am investigating how to access PS_DDR memory from PS APU and RPU.

Is it possible to access exclusively from each CPU of ARM's A53 and R5 ?

Or can the software on A53 and R5 prioritize each traffic for DDR memory access?

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barriet
Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

You may also find Figure 17-2 on page 446 of the TRM (UG1085 as mentioned above) useful.

If you are looking to allow access to a memory region from the APU (A53'ss) but not the RPU (R5's) or vice-versa, you may find the XMPU block useful. You can find more information on this type of application here:
https://www.xilinx.com/support/documentation/application_notes/xapp1320-isolation-methods.pdf (Isolation Methods in Zynq UltraScale+ MPSoCs)

Cheers,
bt

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calebd
Moderator
Moderator
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Registered: ‎01-09-2019

@tte_yoshida 

Both the RPU and the APU are able to access memory.  Your software would determine who would be accessing DDR at a certain point in time.  When you perform that access your software would be the one to determine priority.  The controller wouldn't necessarily make a priority call based on the source processor.

The diagram on page 29 of UG1085 should be helpful to look at the connections between the RPU/APU and the DDR controller: https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

If that doesn't answer your question, can you expand on what you are asking about?

Thanks,

Caleb


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barriet
Xilinx Employee
Xilinx Employee
273 Views
Registered: ‎08-13-2007

You may also find Figure 17-2 on page 446 of the TRM (UG1085 as mentioned above) useful.

If you are looking to allow access to a memory region from the APU (A53'ss) but not the RPU (R5's) or vice-versa, you may find the XMPU block useful. You can find more information on this type of application here:
https://www.xilinx.com/support/documentation/application_notes/xapp1320-isolation-methods.pdf (Isolation Methods in Zynq UltraScale+ MPSoCs)

Cheers,
bt

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