FPGA acting as DDR3 or 4 SDRAM

[min16]

We are trying to make a custom board which goes to DDR3 or 4 DIMM slot and receive signals from the DDR3/4 controller. This device should be shown just like any other SDRAM. We will use DDR3 or DDR4 based on the difficulty to build this board.

I guess we should start from designing a module which takes a DDR signals and translate to AXI (just opposite of MIG) but we wanted to know if there is any similar work done or failed because of some limitations.

Here are the posts I've already seen but I couldn't really get useful information.

https://forums.xilinx.com/t5/UltraScale-Architecture/Can-DDR4-PHY-IP-stand-alone-support-both-master-and-slave/td-p/663589

https://forums.xilinx.com/t5/7-Series-FPGAs/How-to-implement-a-DDR3-SDRAM-function-in-FPGA/td-p/366485

https://forums.xilinx.com/t5/Welcome-Join/DDR3-DQ-Capture-using-FPGA/td-p/361259

Thanks.

[dpaul24]

We have built a device with Artix 7 that pushing data to 8GB DDR3 RAM and reading it back from there. The MIG core in native interface mode has been used. On top of the MIG core is sitting the Xilinx Virtual FIFO controller IP that is managing stuff.

Instead of native_interface an AXI i/f can be used, I don't see any problems with that. All you need is a data source to generate AXI data to be written to the DDR* and checker block verifying the read out AXI data .

Proper board design is necessary for the correct interfacing with the DDR* memory. There are strict guidelines to be followed.

[jheslip]

I am not sure I fully understand the question. The only device family that supports DDR4 is UltraScale / UltraScale + so I assume you are using one of these?

With both our DDR3 and DDR4 is you have the option to enable an AXI interface so this is done for you already With regards to the board as @dpaul24 has mentioned the board guidelines for both are not identical so it could be difficult to get a board that will work with both memory types, if you do I suspect some de-rating maybe needed.

The board guidelines are given in UG 583: http://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

and the IP document is PG150: https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

[min16]

Thanks for the answers but my question is if there already an IP that FPGA can act as a DIMM device. 

Here is the example: http://ieeexplore.ieee.org/document/4101085/

And yes, we are trying to build the board based on Ultrascale/Ultrascale+ device but didn't decide exact model. At this point we're thinking of Virtex Ultrascale+.

[jheslip]

not that I am aware of, certainly not as a standard Vivado IP anyway. in this scenario, you want to mount the FPGA on the DIMM card itself is that correct?

[min16]

Yes. If there is no IP ready for this, I'm planning to use RXTX_BITSLICE and RX_BITSLICE to recover the signals from the memory controller. Right now I'm trying to reverse engineer the MIG and implement something in opposite. For the ease of development, probably we will plug the prototype on to another FPGA board and test with MIG. Does this sound feasible?

[mcertosi · Accepted solution]

Hi @min16

Using the FPGA as a DIMM seems feasible in the sense that there is no hardware limitation preventing our FPGAs from receiving a write or read command from a memory controller. I'm concerned that the additional latency of the FPGA will make it very difficult to meet DDR3 or DDR4 JEDEC timing. 

I see your article mentions this and offers a solution :) 

If your application is similar to the one in the IEEE article I don't see any reason why you can't do it! 

The full article suggests that the engineering team making the DIMMnet-2 board had to derate the interface to 100MHz operation on the FPGA <--> memory controller interface. Watch out for additional capacitance/crosstalk/SI problems on the line from the FPGA loading, see if you can mitigate that with an extra amount of ground via stitching on the FPGA. The better trace matching you do, the less jitter I'd expect introduced from delay elements in the memory controller and FPGA. 

I hope this helps, looks like an exciting project if you can overcome the SI issues. 

Regards, 

-M