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Adventurer
Adventurer
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Registered: ‎03-02-2015

Fail to write data from app_wdf_data signal to ddr3_dq_fpga

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Hi,

 

 

I have two doubts regarding writing data from app_wdf_data to ddr3_dq_fpga.I think,i followed the timing cycle for back to back write transactions given in ug586.

 

1) I am trying to write a sequence of (27'ha,27'hb,27'hc,27'hd,27'he,27'hf,27'hab,27'habc) from app_wdf_data to ddr3_dq_fpga.It is not getting written & some garbage values(222222,333333,999999 etc...) are getting written.

 

2) Ok,consider that garbage values in ddr3_dq_fpga which are getting written,when i try to read from ddr3,those values would be read out naturally.But those values are getting read in reverse order ?Why is this ?

 

Snapshot1:app_wdf_data

Snapshot2:ddr3_dq_fpga

Snapshot3:app_rd_data

app_wdf_data.PNG
ddr3_dq_fpga.PNG
app_rd_data.PNG
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Adventurer
Adventurer
15,509 Views
Registered: ‎03-02-2015

Hi,

 

 

The signal not getting written from app_wdf_data to ddr3_dq_fpga is my fault as i made a mistake with app_wdf_end in write timing diagram.

 

Though that problem of above mentioned wierd data still persists,the main question of this thread has been solved.

 

Thanks,

 

View solution in original post

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Adventurer
Adventurer
8,685 Views
Registered: ‎03-02-2015

Hi,

 

For the above mentioned problem,i was thinking that maybe i'm not exactly following the timing cycles as given in ug 586.

Some of my above problems are same as ones mentioned in :Problems-in-Example-Design-Simulations  & custom-traffic-suggestions thread,but i couldn't understand they solved their problems.

 

So,

1) I ran the example xilinx design & analyzed his waveform timing diagram with mine.

2) Based on these,should by app_en become high before issuing "write" command ?

 

Snapshot1: Example Design Waveform

Snapshot 2: UG586 Write timing diagram.

example_sim.PNG
write_cycle.PNG
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Adventurer
Adventurer
8,669 Views
Registered: ‎03-02-2015

Hi,

 

That wierd data (222222,333333,999999 etc...) that i'm getting at ddr3_dq_fpga which is at the interface of the fpga & DDR3 memory model is same everytime,no matter the input.

 

Is this because,i'm not following timing diagrams  or do i need to debug inside the ip-core.

 

Thanks

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Adventurer
Adventurer
15,510 Views
Registered: ‎03-02-2015

Hi,

 

 

The signal not getting written from app_wdf_data to ddr3_dq_fpga is my fault as i made a mistake with app_wdf_end in write timing diagram.

 

Though that problem of above mentioned wierd data still persists,the main question of this thread has been solved.

 

Thanks,

 

View solution in original post

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