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Visitor
Visitor
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Registered: ‎04-26-2020

Fpga mig7 ddr3 reading is slow

I want to read data from ddr3 memory,reading works good but it is very slow.
it take 24 clock cycle to set 1 in app_rd_data_valid.
ila screenshot
ila2.png

my mig7 configuration

Vivado Project Options:
   Target Device                   : xc7a35t-ftg256
   Speed Grade                     : -3
   HDL                             : verilog
   Synthesis Tool                  : VIVADO

If any of the above options are incorrect,   please click on "Cancel", change the CORE Generator Project Options, and restart MIG.

MIG Output Options:
   Module Name                     : ddr3contr
   No of Controllers               : 1
   Selected Compatible Device(s)   : --

FPGA Options:
   System Clock Type               : No Buffer
   Reference Clock Type            : Use System Clock
   Debug Port                      : OFF
   Internal Vref                   : enabled
   IO Power Reduction              : OFF
   XADC instantiation in MIG       : Enabled

Extended FPGA Options:
   DCI for DQ,DQS/DQS#,DM          : enabled
   Internal Termination (HR Banks) : 50 Ohms
    



/*******************************************************/
/*                  Controller 0                       */
/*******************************************************/
Controller Options :
   Memory                        : DDR3_SDRAM
   Interface                     : NATIVE
   Design Clock Frequency        : 2500 ps (400.00 MHz)
   Phy to Controller Clock Ratio : 4:1
   Input Clock Period            : 4999 ps
   CLKFBOUT_MULT (PLL)           : 4
   DIVCLK_DIVIDE (PLL)           : 1
   VCC_AUX IO                    : 1.8V
   Memory Type                   : Components
   Memory Part                   : MT41J128M16XX-15E
   Equivalent Part(s)            : --
   Data Width                    : 16
   ECC                           : Disabled
   Data Mask                     : enabled
   ORDERING                      : Normal

AXI Parameters :
   Data Width                    : 128
   Arbitration Scheme            : RD_PRI_REG
   Narrow Burst Support          : 0
   ID Width                      : 4

Memory Options:
   Burst Length (MR0[1:0])          : 8 - Fixed
   Read Burst Type (MR0[3])         : Sequential
   CAS Latency (MR0[6:4])           : 6
   Output Drive Strength (MR1[5,1]) : RZQ/6
   Controller CS option             : Disable
   Rtt_NOM - ODT (MR1[9,6,2])       : RZQ/6
   Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off
   Memory Address Mapping           : BANK_ROW_COLUMN


Bank Selections:
	Bank: 15
		Byte Group T0:	Address/Ctrl-1
		Byte Group T1:	Address/Ctrl-0
		Byte Group T2:	DQ[0-7]
		Byte Group T3:	DQ[8-15]

System_Control: 
	SignalName: sys_rst
		PadLocation: No connect  Bank: Select Bank
	SignalName: init_calib_complete
		PadLocation: No connect  Bank: Select Bank
	SignalName: tg_compare_error
		PadLocation: No connect  Bank: Select Bank

state machine taken from here

https://numato.com/kb/simple-ddr3-interfacing-on-nereid-using-xilinx-mig-7/

 

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Adventurer
Adventurer
324 Views
Registered: ‎05-23-2018

Re: Fpga mig7 ddr3 reading is slow

That is basically expected. DDR-Memory is only performant if you drive it with long bursts, in which you want to handle every word of data.

Basically, assuming your Row is already opened, after every READ, you have some latency before a Burst of some Length (8 for DDR3) arrives. If you only need a single word in that burst, you just wasted 7 transfer cycles. Similar, if you can only start the next transfer after the current one has finished, you'll incur another huge latency.

What you need to do is send the first Read, the second Read, and so on, until RDY drops. Then after a while, you'll receive some data and RDY will rise again. Then you send the next burst. And so on.

It might be a good idea to create a small DMA-Engine to handle all of that. If you want to use AXI, the DataMover is quite simple to use and works reasonably well.

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Visitor
Visitor
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Registered: ‎04-26-2020

Re: Fpga mig7 ddr3 reading is slow

thank you for replay.i will try datamover

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Visitor
Visitor
214 Views
Registered: ‎04-26-2020

Re: Fpga mig7 ddr3 reading is slow

Hello

I have another question

I am trying to read data chunks from mig7 controller.
For example send read command for 5 times,then pause controller for some cycles and then again send read command for 5 times  and then start process again .
But when pause between read command is more then 80 clock cycle,read data is not correct.
What i can to do?why this is happening.

if (read_count<5) begin
app_en <= 1;
if(app_rdy)begin
read_count<=read_count+1; 
app_cmd <= CMD_READ; 
app_addr <= readaddr;
if(readaddr<786424)readaddr<=readaddr+8;
else readaddr<=0;
end

end 
else begin 
app_en <= 0;
cycle_counter<=cycle_counter+1;
end


if (app_rd_data_valid) begin


if(addrdebug<786424)addrdebug<=addrdebug+8;
else addrdebug<=0;
data<=app_rd_data;


end

if(cycle_counter==90) begin 
read_count<=5; 
index<=0; 
cycle_counter<=0;


end
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