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Registered: ‎11-19-2015

General question about MIG (ui_clk) and correct connection to AXI and periphery


im working with Artix 7 (xc7a200tffg1156-2) and designing for an custom board in Vivado 2015.3.
My ambition is to run a microblaze including ddr3 and some pherephial like timer and ethernet_mac.

My Sys_clk_p/n come's with 200MHz on the same bank where my ddr3 is connected.
CLK_REF is connectet to Systemclock of this 200MHz.
So my MIG generates an ui_clk of 100MHz and the ddr3 is clocked with 400MHz.
Additional i create optional clocks like ui_addn_clk with 200MHz (which should be phase alligned to ui_clk right?).

So my question is, what is ui_clk for? Do i have to use it? I'm a bit confused that it can't be disabled.
Can i clock my whole component with ui_addn_clk 200MHz? Or do i have to clk all axi components to 100MHz?
If i run on 200MHz do i have to use a AXI FIFO for connection to MIG or slower AXI "peers", because of the different clk rates?

I would like to clock my microblaze and ethernet_mac at 200MHz to ensure the highest throughput.

I think i've missing some piece or do not catch the whole relationship of information i've got from the documentation (mostly from ug586 MIS and ug472 Clocking).



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Xilinx Employee
Xilinx Employee
Registered: ‎07-11-2011



ui_clk is user interface clock through which commands and data are driven to controller and read data is launched to user.

It is basically teh clock with which controller runs and is 1/2 or 1/4 of memory clock decided by phy to controller ratio(nck_per_clock)


Please refer UG586 command, write and read timing diagrams which are mainly based on ui_clk.

If you are using AXI then its write and read ports should be clocked with ui_clk.


If you want to have 200 Mhz as ui_clk/axi clock either increase memory operating frequency to 800 MHZ leaving nCK_per_clock = 4

or make nCK_PER_CLOCK = 2 . with 400 Mhz memory clock.


Hope this helps



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Registered: ‎11-19-2015

Thanks for you fast response.

I can't change to nCK_per_clock = 2 it's greyed out. Probably of my speedgrad 2 ?
My operating frequency is 400MHZ / 2500ps  my range is between 2500 and 3200 (or 3500).
If operation at 400MHz / 2500ps i can't change nCK_per_clock. There is no possible constellation where I can set ddr3 clk to 800. I will look tomorrow (have no license here at home), but i belive there was none. Any further Ideas?
I'am right that i could use a FIFO for Interconnect AXI with diffrent clk rates ? Or is there any other way to interconn different axi (with different clk rates) ?

Found this one, about speedgrades is there any possbility for 800MHz?

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