Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎11-28-2016

Getting Started in the Memory Interfaces Community

Welcome to the Memory Interfaces Community!

When creating a new topic please include helpful information like:

  • FPGA Device Family - 7-Series, Zynq-7000, Kintex UltraScale, Zynq MPSoC, Versal Prime, etc
  • The memory technology and target topology information like UltraScale PL MIG DDR4, 64-bit DIMM, 1866Mbps, AXI interface
  • The Vivado version and the OS information like Vivado 2018.2 and RHEL 7.4 64-Bit
  • Text or screenshots of the logs or error messages
  • Screenshots, ILA captures, or waveforms of the behavior in question
  • Make sure the new topic has a clear and descriptive title

Other helpful tips for a productive community:

  • Instead of asking your question as a new reply in an existing old thread, create a new topic instead
  • Creating a new topic increases the visibility of your question and will be more likely to receive constructive engagement from the community
  • Remember to Kudo good replies in a topic
  • If a reply in your topic was instrumental in resolving your question then mark the post as the Accepted Solution
  • It's always helpful to include a follow up post letting people know when your issue is resolved

Memory Interface Important Answer Records:

Important Documentation for Xilinx Memory Interfaces:

1 Reply
Registered: ‎06-29-2011

Great tips and content for the community to get started with memory interfaces.




Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs