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garengllc
Voyager
Voyager
8,681 Views
Registered: ‎04-10-2012

Getting a translate error for "same direction buffers"

Trying to get MIG to work in a design (my first attempt).  I told it that i have a singe-ended clock and I ged it my 200MHz system clock that I use everywhere else.  Now I get this:

 

ERROR:NgdBuild:770 - IBUFG 'se_input_clk.u_ibufg_sys_clk' and BUFG 'clkout1_buf'
   on net 'CLK_200MHZ' are lined up in series. Buffers of the same direction
   cannot be placed in series.
ERROR:NgdBuild:462 - input pad net 'CLK_200MHZ' drives multiple buffers:
ERROR:NgdBuild:924 - input pad net 'CLK_200MHZ' is driving non-buffer
   primitives:

 I tried goign into the DCM that creates my 200MHz clock and creating another clock that is also 200MHz but doesn't go through a BUFG, but that doesn't seem to help any.  What am I missing here?

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6 Replies
muravin
Scholar
Scholar
8,672 Views
Registered: ‎11-21-2013

What is the next line after:
ERROR:NgdBuild:924 - input pad net 'CLK_200MHZ' is driving non-buffer
primitives:

It looks like there are IBUFG driving IBUFG or BUFG driving IBUFG etc. Or sometimes I saw people's using IBUFG then BUFGP, which is also not good.
Vladislav Muravin
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gszakacs
Professor
Professor
8,663 Views
Registered: ‎08-14-2007

The MIG design has an "infrastructure" module that has the input clock buffering in it.  If you want to use an existing global clock, you need to edit this module to remove the input buffer.  Normally your only choice is "single-ended" or "differential" and MIG expects the pin (top level clock input port) to connect directly.

 

Another way around this is to run your clock pin to MIG and use a MIG output clock to run 200 MHz to the rest of your design.  However that presumes that MIG provides such an output.  Otherwise you're back to editing the "infrastructure" module.

 

A note of caution when editing MIG-generated files:

 

Make a copy of the files you want to edit in another folder and edit the copy.  Then remove the original from the design and add the edited copy.  Otherwise if you ever need to re-build the MIG core your edits will be lost.

-- Gabor
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yenigal
Xilinx Employee
Xilinx Employee
8,654 Views
Registered: ‎02-06-2013

 

Hi

 

What is the device you are using?

 

I suspect that in the clocking wizard the generated clock is driving  BUFG(which will be default option) and causing this issue.

 

Select NO buffer option in the GUI

 

Also check below AR's for the procedure to do clock modifications.

 

http://www.xilinx.com/support/answers/35242.html

http://www.xilinx.com/support/answers/43559.html

Regards,

Satish

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garengllc
Voyager
Voyager
8,639 Views
Registered: ‎04-10-2012

You guys are right, it is due to the lower level expeting external clock inputs.  I went into iodelay_ctrl.v and clk_ibuf.v and disabled the IBUFG sicne it isn't an input clock controlling it, but something created internally.  

 

That gets past that issue, but causes another (isnt' that always the case).  I end up with a PLACE:1131 error for cascaded BUFGCTRL clocks.  To try to clean that up, I passed the 200MHz clock through another clock wizard, and then through a BUFR thinking that it might allow things to be routable since there are more stanges there, but no dice.  i get the same error:

ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component pair have been found that are not placed at
   a routable site pair. The driver BUFGCTRL component <clock_distribution/CLK_100MHZ_200MHZ/clkout1_buf> is placed at
   site <BUFGCTRL_X0Y17>. The load BUFGCTRL component <clockBuffer200MHz/clkin1_buf> is placed at site <BUFGCTRL_X0Y30>.
   The BUFGCTRL components can use the fast path between them if they are placed in adjacent BUFGCTRL sites, and both
   are in the same half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct it.
   This placement is UNROUTABLE in PAR and therefore, this error condition should be fixed in your design. You may use
   the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD
   file. This NCD file can then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in the .ucf file to demote this ERROR to a
   WARNING.

 

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gszakacs
Professor
Professor
8,633 Views
Registered: ‎08-14-2007

It sounds like you removed the input buffer but not the global clock buffer.  In any case you never said which device you're using.  MIG is a completely different animal for each FPGA family, so the answer to your problem will depend on the device family.

-- Gabor
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garengllc
Voyager
Voyager
8,631 Views
Registered: ‎04-10-2012

Yikes, you are right on all accounts.  I am using a V6 and ISE.

 

I got rid of the BUFG in iodelay_ctrl.v and am trying again.

 

This is my first attempt at MIG and it has a bit (an understatement) more of a learning curve than I expected!

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