UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor cmurphy1212
Visitor
492 Views
Registered: ‎07-03-2019

HBM Debug Hub Clock

Jump to solution

Hello,

The HBM IP automatically inserts a debug core with two probes, one for each stack. However, I have observed the debug hub defaults to using a 250MHz AXI clock present in the design (not the reference design), rather than one of the HBM's 100MHz APB clocks. This causes severe WHS issues since it appears the APB logic inside each ONE_STACK HBM IP is not set up to cross domains from its own APB clock to the domain used by the debug hub.

When I force the debug hub to use one of the APB clocks, it cleans up the hold violations using the following constraint:

connect_debug_port dbg_hub/clk [get_nets *APB_0_PCLK]

However, this is still not ideal, since each stack has it's own APB clock, I would prefer to have APB logic present in each stack to use the clock relevant to it's own side, not be forced into using an APB clock from a single side, or worse defaulting to the AXI clock. Since the probes are added automatically, I am unable to determine how I would configure a second debug hub, and I have no guarantee that the Activity Monitor would still work in such a custom scenario.

Can anyone provide insight into how the HBM IP expects to have the debug hub configured? I would like to associate each of the HBM debug probes with their most relevant clock. Finally, perhaps this is not a necessary path to go down. In that case, can anyone confirm the intended clock for the debug hub in light of the fact that there two different APB clocks present in a two-stack HBM design?

 

Thanks

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
387 Views
Registered: ‎11-28-2016

回复: HBM Debug Hub Clock

Jump to solution

Hello @cmurphy1212 ,

In the last few Vivado releases there have been some changes as to how the HBM IP deals with the debug hub clocking.  In 2019.1 it should be selecting the APB clock automatically unless you're in IPI then you'll have to manually connect the APB clock to the debug hub.  For this scenario you would see an error at implementation that the debug hub clock was not connected.

Regarding the scenario when you have both HBM stacks enabled the tools will still try to connect a single APB clock to drive a single debug hub that's accepting both of the debug core's signals from the stacks.  This also isn't ideal as you've already pointed out.  Internally we are looking at this behavior and I'm hoping for some clarity on the best approach for this.  At the moment the guidance is still to let the tools automatically handle this since the tools don't like user intervention in this area.  Looking at the current situation I expect one AR to be released for the debug hub connection behavior in IPI and my hope is things are cleaned up a bit more for the dual stack scenario in 2019.2.

Tags (1)
5 Replies
Xilinx Employee
Xilinx Employee
454 Views
Registered: ‎08-21-2007

回复: HBM Debug Hub Clock

Jump to solution

The clock of the debug hub is chosen by Vivado automatically. I suggest you assign it manually as you did per your requirement.

0 Kudos
Visitor cmurphy1212
Visitor
445 Views
Registered: ‎07-03-2019

回复: HBM Debug Hub Clock

Jump to solution

My understanding is that there can only be one clock per debug hub. The HBM IP behavior with respect to the APB debug ports appears to be undocumented. Can you confirm that the HBM IP was designed to use only one APB clock and ignore the second one?

0 Kudos
Xilinx Employee
Xilinx Employee
424 Views
Registered: ‎08-21-2007

回复: HBM Debug Hub Clock

Jump to solution

Yes, the clock of the debug hub is a free-running clock. It is not required to be the HBM clocks.

0 Kudos
Moderator
Moderator
388 Views
Registered: ‎11-28-2016

回复: HBM Debug Hub Clock

Jump to solution

Hello @cmurphy1212 ,

In the last few Vivado releases there have been some changes as to how the HBM IP deals with the debug hub clocking.  In 2019.1 it should be selecting the APB clock automatically unless you're in IPI then you'll have to manually connect the APB clock to the debug hub.  For this scenario you would see an error at implementation that the debug hub clock was not connected.

Regarding the scenario when you have both HBM stacks enabled the tools will still try to connect a single APB clock to drive a single debug hub that's accepting both of the debug core's signals from the stacks.  This also isn't ideal as you've already pointed out.  Internally we are looking at this behavior and I'm hoping for some clarity on the best approach for this.  At the moment the guidance is still to let the tools automatically handle this since the tools don't like user intervention in this area.  Looking at the current situation I expect one AR to be released for the debug hub connection behavior in IPI and my hope is things are cleaned up a bit more for the dual stack scenario in 2019.2.

Tags (1)
Highlighted
Moderator
Moderator
258 Views
Registered: ‎11-28-2016

回复: HBM Debug Hub Clock

Jump to solution

Hello @cmurphy1212 ,

Just wanted to circle back for an update on this.
In 2019.2 when both HBM stacks are enabled the IP will set a false path constraint between the APB_0_PCLK and APB_1_PCLK clocks so the tools wont' try to time them and you won't get a TIMING-6 or TIMING-7 Critical Warning anymore.

0 Kudos