07-23-2018 07:35 PM - edited 07-25-2018 12:26 AM
I'm using HBM example design to simulate. Everything works well but could you please provide a backdoor way so that I can force data directly to the sim HBM without writing through AXI port? This will help us to initial the HBM with some value.
the backdoor should have this format : // HDL_PATH : + ...hbm_0.inst.u_hbm_top.hbm_two_stack_intf.hbm_mem_rt.mem[index]
07-25-2018 09:33 AM
I have contacted Samsung to see if they have a solution that they can provide us. Currently we do not have a way to pre-load data into the HBM model without the AXI Interface.
07-25-2018 08:46 PM
08-02-2018 07:19 AM - edited 08-02-2018 07:19 AM
No I have not heard anything. I do not think a simulation backdoor exists. The AXI Interface is required to populate the DRAM contents.
02-21-2019 04:27 PM
Does anyone know if there were any actions being taken to change this or if Samsung has provided to you directly?
Really, i don't think Xilinx can consider themselves a serious memory vendor without this ability.