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1,230 Views
Registered: ‎06-16-2018

HBM Simulation Backdoor

Hi Xilinx,

I'm using HBM example design to simulate. Everything works well but could you please provide a backdoor way so that I can force data directly to the sim HBM without writing through AXI port? This will help us to initial the HBM with some value.

the backdoor should have this format : // HDL_PATH  : + ...hbm_0.inst.u_hbm_top.hbm_two_stack_intf.hbm_mem_rt.mem[index]

 

Many thanks.

5 Replies
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Moderator
Moderator
1,153 Views
Registered: ‎02-11-2014

Hello @haiphongpham1995,

 

I have contacted Samsung to see if they have a solution that they can provide us. Currently we do not have a way to pre-load data into the HBM model without the AXI Interface.

 

Thanks,

Cory

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1,143 Views
Registered: ‎06-16-2018

hi @coryb,

Thank you very much for your support. So we'd better wait now. Let me know if you get any information from SamSung.

 

Many thanks

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Highlighted
1,096 Views
Registered: ‎06-16-2018

Hi @coryb,

any information from Samsung yet?

thanks

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Moderator
Moderator
1,078 Views
Registered: ‎02-11-2014

Hello @haiphongpham1995,

 

No I have not heard anything. I do not think a simulation backdoor exists. The AXI Interface is required to populate the DRAM contents.

 

Thanks,

Cory

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Observer
Observer
521 Views
Registered: ‎04-30-2017


Hi,

 

Does anyone know if there were any actions being taken to change this or if Samsung has provided to you directly?   

Really, i don't think Xilinx can consider themselves a serious memory vendor without this ability.

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