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851 Views
Registered: ‎06-16-2018

HBM hard switch low bandwidth

hi all,

I tried to generate an HBM stack with global addressing mode. The measured bandwidth is quite bad (in read write mode, read (7%), write (25%) , continously switching among 4 ports). In RO and WO mode, the result is not much better. Is this the limitation of the hard switch or any hint?

Thanks all

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Moderator
Moderator
761 Views
Registered: ‎02-11-2014

Re: HBM hard switch low bandwidth

Hello @haiphongpham1995,

 

We do not have enough information form you to provide an answer.

 

What kind of traffic pattern are you running? Can you provide a testcase and/or your XCI file? Have you tried using our Example Design build around your core configuration to see if you get better bandwidth?

 

Thanks,
Cory

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Advisor evgenis1
Advisor
593 Views
Registered: ‎12-03-2007

Re: HBM hard switch low bandwidth

Hi @haiphongpham1995

 

I think HBM performance heavily depends on the addressing scheme. 

The reason is that HBM is physically implemented as 8 memory controllers and 4 memory tiles per stack, as shown in the attached screenshots. So if your design continuously writes to the same memory address from all 32 channels, you'd get 1/32th of the peak bandwidth. The peak performance is achieved when accesses are spread out to non-overlapping addresses within address range of each channel (no crossbar accesses).

 

Thanks,

Evgeni

 

 

 

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