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Observer
Observer
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Registered: ‎03-14-2018

HBM simulation with QuestaSim

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Hello,

I 'm trying to simulate HBM  in Vivado 2019.2.1 with QuestaSim.

I defined the 3rd Party Simulators (  QuestaSim directory in install Paths  and a compiled version of libraties path  in default Compiled Librarty paths  : for Questa)

 

I have these errors when I launch the simulation:

# 10.6

# do {HBM_sim_compile.do}

OK

# do {HBM_sim_elaborate.do}
# ** Error: QuestaSim-64 vopt 10.6 Compiler 2016.12 Dec 13 2016
# Start time: 17:37:43 on Mar 02,2020
# vopt "+acc=npr" -L lib_pkg_v1_0_2 -L axi_apb_bridge_v3_0_16 -L xil_defaultlib -L hbm_v1_0_6 -L unisims_ver -L unimacro_ver -L secureip -L xpm -work xil_defaultlib xil_defaultlib.HBM_sim xil_defaultlib.glbl -o HBM_sim_opt
#
# Top level modules:
# HBM_sim
# glbl
#
# Analyzing design...
# -- Loading package STANDARD

.......

# ** Error: D:\Xilinx\vivado\Vivado\2019.2\data\secureip\hbm_one_stack_intf\hbm_one_stack_intf_001.sv(37110): Module 'xil_hbm_one_stack_intf_mod0' is not defined.
# ** Error: D:\Xilinx\vivado\Vivado\2019.2\data\secureip\hbm_one_stack_intf\hbm_one_stack_intf_001.sv(37120): Module 'xil_hbm_one_stack_intf_mod786' is not defined.
# ** Error: D:\Xilinx\vivado\Vivado\2019.2\data\secureip\hbm_one_stack_intf\hbm_one_stack_intf_001.sv(39878): Module 'xil_hbm_one_stack_intf_mod1' is not defined.

# -- Loading module HBM
# Optimization failed
# ** Warning: (vopt-133) Unable to remove directory "Z:/DAQ_4_DAQ_p2/Kit/FPGA/DTH_HBM_sim/top.sim/sim_1/behav/questa/questa_lib/msim/xil_defaultlib/@h@b@m_sim_opt".
# End time: 17:37:45 on Mar 02,2020, Elapsed time: 0:00:02
# Errors: 3, Warnings: 1
# child process exited abnormally
# Error in macro ./HBM_sim_elaborate.do line 9
# QuestaSim-64 vopt 10.6 Compiler 2016.12 Dec 13 2016

# Top level modules:
# HBM_sim
# glbl
#
# Analyzing design...
# -- Loading package ST

# -- Loading module secureip.SIP_HBM_ONE_STACK_INTF
# ** Error: D:\Xilinx\vivado\Vivado\2019.2\data\secureip\hbm_one_stack_intf\hbm_one_stack_intf_001.sv(37110): Module 'xil_hbm_one_stack_intf_mod0' is not defined.
# ** Error: D:\Xilinx\vivado\Vivado\2019.2\data\secureip\hbm_one_stack_intf\hbm_one_stack_intf_001.sv(37120): Module 'xil_hbm_one_stack_intf_mod786' is not defined.
# ** Error: D:\Xilinx\vivado\Vivado\2019.2\data\secureip\hbm_one_stack_intf\hbm_one_stack_intf_001.sv(39878): Module 'xil_hbm_one_stack_intf_mod1' is not defined.
# -- Loading module HBM
# Optimization failed
# ** Warning: (vopt-133) Unable to remove directory "Z:/DAQ_4_DAQ_p2/Kit/FPGA/DTH_HBM_sim/top.sim/sim_1/behav/questa/questa_lib/msim/xil_defaultlib/@h@b@m_sim_opt".
# End time: 17:37:45 on Mar 02,2020, Elapsed time: 0:00:02
# Errors: 3, Warnings: 1
# child process exited abnormally
# while executing
# "exec <nul: {D:\EDA\questasim64_10.6\win64\vopt.EXE} -64 +acc=npr -L lib_pkg_v1_0_2 -L axi_apb_bridge_v3_0_16 -L xil_defaultlib -L hbm_v1_0_6 -L unisim..."
# ("uplevel" body line 1)
# invoked from within
# "uplevel 1 exec $redir $new [lrange $args 1 end]"
# (procedure "::unknown" line 47)
# invoked from within
# "D:\\EDA\\questasim64_10.6\\win64\\vopt -64 +acc=npr -L lib_pkg_v1_0_2 -L axi_apb_bridge_v3_0_16 -L xil_defaultlib -L hbm_v1_0_6 -L unisims_ver -L unim..."

 

 

What do I do wrong? or miss?

Thanks

Regards

Dominique

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Xilinx Employee
Xilinx Employee
417 Views
Registered: ‎08-21-2007

Please check the secureip libraries are all compiled. Also upgrade to Questasim 2019.2 to ensure correct simulation.

View solution in original post

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Xilinx Employee
Xilinx Employee
418 Views
Registered: ‎08-21-2007

Please check the secureip libraries are all compiled. Also upgrade to Questasim 2019.2 to ensure correct simulation.

View solution in original post

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Highlighted
118 Views
Registered: ‎07-05-2019

what‘s the problem finally?

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