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Adventurer
Adventurer
6,318 Views
Registered: ‎01-13-2012

HW cosimulation on MIG design on VIrtex 5

Hello,

 

I have a virtex-5 board and I used the CoreGen to generate a memory controller interface to an on-board DDR2. The design comes with a synthesizable test bench. I am a bit confused about how this testbench is used or how to use it. Is it for hw co-simulation? I believe it is. However, for some reason, I cannot do a hw co-simulation using iSim on ISE 14.4. I have a Xilinx System edition license, and have access to all the tools. Hence, I doubt if this is a license issue.Looking at the reference guide : http://www.xilinx.com/tools/feature/14_1_isim_hw_cosim_qrg.pdf, I observe that my directory to $XILINX/sysgen is empty.

 

Any suggestions would be useful.

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Xilinx Employee
Xilinx Employee
6,305 Views
Registered: ‎02-06-2013

Hi

 

The example design and the test bench delivered with MIG are to assist with easy testing on the Hardware and to make it easy for customers to modify it for thier custom applications.

 

It is nothing to do with HW cosimulation.

Regards,

Satish

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Adventurer
Adventurer
6,291 Views
Registered: ‎01-13-2012

I don't understand then how the testbench is supposed to be used for testing on the hardware other than hw co-simulation. When I install the bitstream onto my FPGA, how can I use the testbench provided? Thanks.

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