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harshalrode
Contributor
Contributor
2,974 Views
Registered: ‎10-01-2009

Has anyone implemented mig ddr controller on spartan 3E kit

Hi

 

Has anyone used mig design for spartan 3E kit for SDRAM read-write.

How do we modify the code to use in FPGA for our application.

 

Thank you

Harshal

 

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criley
Xilinx Employee
Xilinx Employee
2,917 Views
Registered: ‎08-16-2007

Are you using MIG as your interface controller? If so MIG generates RTL that you can modify including a UCF constraints file that you can modify to meet the Kit's pinout requirements.

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