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Explorer
Explorer
419 Views
Registered: ‎12-07-2018

Help setting IO Std for DDR4 Pins

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Hello, I am a newbie with Vivado and am doing a design with DDR4. I have connected all the DDR4 IO to the BGA pins and now I'm getting some errors relating to the IO standard for certain pins. Is there a document that states what IO setting one should use for the DDR4 signals:

DDR4_act_n
DDR4_dq
DDR4_odt
DDR4_dqs
DDR4_ck
DDR4_dm

DDR4_IO_Std.jpg

 

Here is an error message I get after I run the Implentation:

[DRC PORTPROP-6] I/O standard compatibility with attribute usage: Port PL_DDR4_act_n has property EQUALIZATION set, but its I/O Standard, SSTL12_DCI, does not support this property.
[DRC PORTPROP-6] I/O standard compatibility with attribute usage: Port PL_DDR4_act_n has property OFFSET_CNTRL set, but its I/O Standard, SSTL12_DCI, does not support this property.
[DRC PORTPROP-6] I/O standard compatibility with attribute usage: Port PL_DDR4_act_n has property PRE_EMPHASIS set, but its I/O Standard, SSTL12_DCI, does not support this property.

I need some help getting rid of this error message and help configuring the DDR4 pins to the appropriate IO settings.

 

Thank you very much,

Joe

 

1 Solution

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Xilinx Employee
Xilinx Employee
329 Views
Registered: ‎03-04-2018

Re: Help setting IO Std for DDR4 Pins

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Hello @joe306 ,

 

The most easiest way is to refer an example design. 

Do you use an UltraScale/UltraScale+ device?  If so, the example design is described in the PG150, from page.242.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

UG571 explains the select io like SSTL_12_DCI, so it would be useful.

https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

 

 

Best regards,

Kshimizu

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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3 Replies
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Xilinx Employee
Xilinx Employee
330 Views
Registered: ‎03-04-2018

Re: Help setting IO Std for DDR4 Pins

Jump to solution

Hello @joe306 ,

 

The most easiest way is to refer an example design. 

Do you use an UltraScale/UltraScale+ device?  If so, the example design is described in the PG150, from page.242.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

UG571 explains the select io like SSTL_12_DCI, so it would be useful.

https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

 

 

Best regards,

Kshimizu

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

-------------------------------------------------------

View solution in original post

Xilinx Employee
Xilinx Employee
316 Views
Registered: ‎08-21-2007

回复: Help setting IO Std for DDR4 Pins

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As you have DDR4 IP in your design, the IO standard contraints are created by IP. You only have to assign the memroy IO location constraints in your top xdc file.

Explorer
Explorer
242 Views
Registered: ‎12-07-2018

回复: Help setting IO Std for DDR4 Pins

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Thank you very much. 

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