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Adventurer
Adventurer
11,455 Views
Registered: ‎08-08-2009

How can I control 2 DDR2 modules in 1 FPGA chip by using MIG IP core?

I use XC5VLX220-1FF1760, MT4HTF3264HY-53E, ISE v12.1, MIG v3.4.

I choose multicontrollers 2 in one MIG to control 2 MT4HTF3264HY-53E modules ( in one FPGA chip ) , and thus it generates 2 groups of user application signals and memory device signals.

I found clk0_tb, rst0_tb and ddr2_reset_n signals public used.

Can I control 2 MT4HTF3264HY-53E modules in the way above ?

If can't ? How can I do ? Thanks !

 

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Moderator
Moderator
11,446 Views
Registered: ‎08-21-2007

Yes, the two DDR2 controllers are independent. You can modify the source code and get clk0_tbrst0_tb and ddr2_reset_n signals driven by differential signals.

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Adventurer
Adventurer
11,445 Views
Registered: ‎08-08-2009

Oh, thank you very much!  :smileyhappy:

Can I use two IP cores to control partly two DDR chips ?

And comparing with my first method, which is better ?

But I meet a problem that I can't solve ( using my first method ( one IP Core control two DDR2 modules ) ):

ERROR:LIT:600 - IOBUFDS symbol
   "u_ddr2/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/gen_dqs_iob_ddr2.u_iobuf_dqs" (output
   signal=u_ddr2/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_d
   qs/dqs_ibuf) does not have IOSTANDARD specified. Map is unable to generate a
   default IOSTANDARD for IOBUFDS, one has to be explicitly provided.

 

How can I solve this prolem?

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Explorer
Explorer
11,005 Views
Registered: ‎03-25-2010

Hello,

 

I am having the same error that you had. Did you solved it?

 

ERROR:LIT:600 - IOBUFDS symbol
   "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/gen_dqs_iob_ddr2.u_iobuf_dqs" (output
   signal=DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
   qs[0].u_iob_dqs/dqs_ibuf) does not have IOSTANDARD specified. Map is unable
   to generate a default IOSTANDARD for IOBUFDS, one has to be explicitly
   provided.

 

Thanks.

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Instructor
Instructor
11,003 Views
Registered: ‎07-21-2009

The simple answer is to use Planahead (or edit .UCF manually) to specify an IOSTANDARD parameter for the DQS output diff pair.  It should be the same as for the DQ pins.

 

- Bob Elkind

SIGNATURE:
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Highlighted
10,836 Views
Registered: ‎11-29-2010

 

I have tried to may my design  with DDR2 modules into a V5LX50T FPGA using ISE 12.3. However I get the following error:  
Error: LIT 600 - IOBUFDS
 "Inst_system/DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dqs[0].u_iob_dqs/gen_dqs_iob_ddr2.u_iobuf_dqs" 
(output signal=
Inst_system/DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dqs[0].u_iob_dqs/dqs_ibuf) 
does not have IOSTANDARD specified. Map is unable to generate a default IOSTANDARD for IOBUFDS, one
   has to be explicitly provided.
Errors found during logical drc. 
Design Summary
--------------
I have tried to edit the .ucf file manually and set the DQS pins with the same parameter as that of the DQ pins, but no use. Could anyone let me know as to how can I figure out this problem.
Regards

 

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Instructor
Instructor
10,830 Views
Registered: ‎07-21-2009

Vijay,

 

Your problem seems to be the same as the original post's example.  The suggested remedy is the same as well.

 

Specify the proper IOSTANDARD for the IOBUFDS package pins.  You can do this by either manually editing the .UCF file for your design, or use the PLANAHEAD tool to make the changes.  The proper IOSTANDARD for differential DDR2 signals is DIFF_SSTL18_II.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor
Visitor
9,794 Views
Registered: ‎06-14-2011

I'm fairly new to FPGAs and I want to make sure I understand this.

 

I had this exact same error.

 

but my UCF file had theses lines in it :

 

NET  "ddr2_dqs[*]"                              IOSTANDARD = DIFF_SSTL18_II_DCI;

NET  "ddr2_dqs_n[*]"                            IOSTANDARD = DIFF_SSTL18_II_DCI;

 

which sounds like your answer - no ?

 

I got past the problem by adding the IOSTANDARD line to the code in ddr2_phy_dqs_iobs.v file :

 

  generate
    if (DDR_TYPE > 0) begin: gen_dqs_iob_ddr2
      IOBUFDS #
        (
         .IOSTANDARD ("DIFF_SSTL18_II_DCI")
        )
        u_iobuf_dqs
        (
         .O   (dqs_ibuf),
         .IO  (ddr_dqs),
         .IOB (ddr_dqs_n),
         .I   (dqs_out),
         .T   (dqs_oe_n_r)
         );
    end else begin: gen_dqs_iob_ddr1
      IOBUF u_iobuf_dqs
        (
         .O   (dqs_ibuf),
         .IO  (ddr_dqs),
         .I   (dqs_out),
         .T   (dqs_oe_n_r)
         );
    end
  endgenerate

 I'm not crazy about this solution and would appreciate a better approach to fixing the error.

 

Thanks in advance.

 

Martin

 

P.S.

 

I doubt these particulars matter for this question, but will include them just in case.

 

I used MIG  3.61.

Target FPGA is Virtex 5.

FPGA : xc5lvx110-ff1153

UDIMM - MT4HTF3264AY-667

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Newbie
Newbie
8,637 Views
Registered: ‎06-11-2013

i often meet the same poblem

when i meet this problem i will rebuild a new project and maybe this problem don't appear again

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Newbie
Newbie
7,848 Views
Registered: ‎03-18-2014

Where did you find this file?

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