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Visitor
Visitor
7,231 Views
Registered: ‎05-07-2014

How do I get MIG DQS book for my design?

I have some existing FPGA boards where the DQS lines to the DDR are connected to DQS  pins on the FPGA. This works fine if I use a MIG design to drive the DDR. However, I need to prototype an application using these same boards but with a custom DDR driver. It appears that the DQS pin on the FPGA does not act as a DQS driver if a MIG is not used. (The internal delay {PHASOR?] of the DQS driver is not used. Instead wiring is run to an external delay book and this causes excessive delay, enough to cripple the interface.

 

I cannot rework the boards (the connections I need are not accessible). I also cannot use a MIG driver, since the interface to the core logic in the FPGA is not a standard interface.

 

Is there a way I can get the DQS function on the FPGA DQS pin when I use a custom driver?

 

Thanks.

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Xilinx Employee
Xilinx Employee
7,207 Views
Registered: ‎08-16-2007

The PHASER's and other hardened blocks in the MIG PHY are only supported using MIG but you do have a few other options. You can use the PHY only portion of the MIG design which we have documented in UG586 and also in AR51204. This will allow you to create your own memory controller logic that connects up to the MIG PHY.

 

The other option is you can develop your own completely soft memory controller (uses fabric logic instead of any hardned blocks and PHY logic). This will have to be created and completely developed on your own though. You can then use the IODELAY elements on DQS for calibration.

 

 

UG586: http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf

AR51204: http://www.xilinx.com/support/answers/51204.html