10-18-2020 10:54 PM
Hello
I tried to use DDR and HBM at the same the on vcu128 board,The message indicates an error in the constraint file for DDR, but the file is read Only. I tried the solution for this page
The IP setting and logs are below. Please tell me the correct way to build IP.
10-18-2020 10:55 PM
logs are shown in pic 2
10-18-2020 11:54 PM
Hello @xifengw ,
The output from clk_wiz is connected to the DDR4(MIG) in your design. The MMCM output is not used as the sys_clk in DDR4(MIG). System clock needs to use the GCIO pin.
Attached is from the PG150 which describes the MIG.
Best regards,
Kshimizu
Product Application Engineer Xilinx Technical Support
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10-19-2020 01:32 AM