How to access the mode register of DDR4 IP via DDR4 UI?

[weishenmewhy1]

I use the Vivado 2017.3 to create a DDR4 IP for NVDIMM, and the example pattern just write some data into the DDR4 SDRAM and read them back, but I need to access DDR4 SDRAM mode registers in my own design. could anyone help me on how to access the mode registers (MR0~MR7)? many thanks in advance.

[jheslip]

you can read the mode registers from the IP code is that what you want or do you want to read it from the memory device?

I assume you are using the Custom CSV file to support this device?

[weishenmewhy1]

thanks for your reply and sorry to make you confused.  I draw the attached picture for my question.  I use the Vidado tool and generated a RDIMM IP , how could the host(FPGA) configure(write and read) the mode registers inside DDR4 SDRAM via the DDR CORE UI (APP_BUS)? 

The app_bus is the user interface between FPAG and DDR CORE. and it contain (app_addr[30:0]、app_cmd[2:0])、app_en、app_hi_pri、app_autoprecharge、app_wdf_data[511:0] ...) . the example pattern just write and read the RAM inside DDR4 SDRAM， not write and read mode registers inside DDR4 SDRAM. therefore, I do not which value shall I send to the app_bus. 

[mcertosi]

Hi @weishenmewhy1

The Xilinx memory IP does not have a feature that allows users to send mode register commands or writes via the app_* interface. 

The IP was designed to target a static configuration and because of that, the only way to control what is programmed in the mode registers is to change the RTL. 

Have you looked around in the RTL at all? 

Would you application require changing mode register values on the fly? If not, then you likely don't need to do anything with the mode registers as they are auto-generated for the Xilinx preferred values based on the target configuration and our IP characterization during development. 

Thanks,

M

[weishenmewhy1]

Hi @mcertosi

thanks and possibly my application need configure the mode registers on the fly.

and as the picture shows there is a RCD between DDR4 device and DDR_CORE, is it possible to configure the RCW registers in RCD via APP_* interface as well? if no, How could I configure both the mode register and RCW registers on the fly? thanks in advance.

[mcertosi]

Hi @weishenmewhy1

There is no Xilinx provided feature to program the RCD on the fly. If you'd like to do this, you'll need to implement this feature yourself.

Can you describe a scenario where you have the IP up and running and then need to reprogram the RCD? Try to include as many details as possible.

-M

[weishenmewhy1]

Hi @mcertosi

the scenario is that in a NVDIMM mode, NV controller need to program mode register and RCD Control Word before/during/after SAVE&RESTORE process as the JESD245B-01 "ANNEX A (normative) SDRAM and RCD Requirements for NVRDIMM-N modules" describes. since there are so many steps I just copy some steps out.

2.19.3       Save Mode Exit Sequence

The recommended sequence to exit Save Mode in an NVDIMM using the NV mode features of the DDR4RCD02 and DDR4DB02 devices is shown below.

1. NV controller finishes saving DRAM data in Non-Volatile Memory.
2. NV controller restores DDR4RCD02/DDR4DB02 (and DRAM) settings it has modified (as needed).
3. NV controller puts active DRAMs in Self Refresh state.
4. NV controller gives RCD control back to the Host (F4RC00.DA[2:1]=00b).
5. NV controller drives LCKE Low and disables LCK_t/LCK_c and LCOM[2:0] drivers.   

[mcertosi · Accepted solution]

Hi @weishenmewhy1

Unfortunately there is no way to write to the mode registers through our app_* interface. 

Since the DDR4 controller isn't an NVDIMM controller we don't have this feature built in. 

Our controller uses the microblaze for MPR writes and initialization. That means you won't have much luck using the existing RTL as a guide, however there are some tasks in there for MPR initialization that could help you get started. 

The Microblaze in the IP is locked, so you might have to add your own microblaze to implement an MPR writing function should you want to go that route. 

I'm not sure how helpful this is, sorry we don't have a better solution here.

-M

[weishenmewhy1]

Hi @mcertosi

many thanks for your time.