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Adventurer
Adventurer
1,151 Views
Registered: ‎01-20-2017

How to adjust IOStandard for sys_rst

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I used the MIG tool to generate a project and I'm using the example design to debug the memory interface.  I'm running into a situation where the Bank corresponding to the sys_rst signal generated by the MIG is powered via a 3.3V VCCO.  However, the MIG XDC file ID's this pin with a LVCMOS25 IOStandard.  When I try to generate a bitstream, I get the error:

 

  • [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 13. For example, the following two ports in this bank have conflicting VCCOs: sys_rst (LVCMOS25, requiring VCCO=2.500) and testp[1] (LVCMOS33, requiring VCCO=3.300)

 

I'd like to set this to LVCMOS33 (b/c I use it for some other signals on the board (namely the testp[1] signal identified above)) - but I can't edit the XDC file created by the MIG tool.  

 

I checked the SelectIO resources doc.  As this is an HR Bank, it seems fine to drive it with either LVCMOS25 or LVCMOS33.  So I don't think I'm violating anything there.

 

My FPGA is an Artix 7 XC7A100TFGG484 part and I'm working in Vivado 2016.2

 

How can I adjust this IOSTANDARD level to use LVCMOS33 in the MIG?

 




 

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Xilinx Employee
Xilinx Employee
1,100 Views
Registered: ‎09-20-2012

Hi @efpkopin

 

You  can specify IOSTANDARD constraint on port which drives sys_rst MIG input in your top level XDC file. This constraint will override the one present in IP XDC.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
1,101 Views
Registered: ‎09-20-2012

Hi @efpkopin

 

You  can specify IOSTANDARD constraint on port which drives sys_rst MIG input in your top level XDC file. This constraint will override the one present in IP XDC.

Thanks,
Deepika.
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Mentor
Mentor
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Registered: ‎10-07-2011

Hi @efpkopin 

I have the exact same concern. Did you try Deepika's solution? Is it working?

Thanks!

Claude

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Registered: ‎01-22-2015

@chevalier 

-just a few thoughts in case efpkopin does not answer:

  1. Although not with MIG IP, I have successfully used constraints in the master XDC file for a Vivado project to override constraints in the XDC file associated with IP.  So, Deepika's suggestion should work.

  2. Vivado guesses(!) the value of VCCO for each FPGA bank based on the IOSTANDARDs that you specify for pins in the bank.  That is, there is no direct way to tell Vivado the value of VCCO.  So, for a board with a bank VCCO=3.3V, if you accidently use IOSTANDARD=LVCMOS25 in Vivado for all pins in the bank then Vivado would simply guess that VCCO=2.5V and give you no warnings.  This is dangerous and could lead to damage of the FPGA.

  3. Vivado will warn you if you start mixing incompatible IOSTANDARDs.  Some IOSTANDARDs are obviously incompatible (eg. LVCMOS25 and LVCMOS33).  However, some IOSTANDARDs are not obviously incompatible.  For 7-Series devices, see page 97 of UG471(v1.10) for a list of IOSTANDARD compatibility rules.  

So, if Deepika’s solution doesn’t seem to be working then maybe you’ve got a nonobvious incompatibility of IOSTANDARDs and Vivado is guessing the wrong VCCO for the IO bank.

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Adventurer
Adventurer
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Registered: ‎01-20-2017

@chevalier, I apologize, it's been a while since I've worked with that particular project.  So I can't remember all the details.  However, I just took a look at the project files and consulted my notes, and I did indeed set the IOSTANDARD for that pin as LVCMOS33.  So my suspicion is that this worked (my apologies to the community at large for not accepting vemulad's solution at the time).

 

HTH

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