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tomray
Observer
Observer
7,000 Views
Registered: ‎03-27-2014

How to avoid the initialization process when simulating with DDR3 MIG memory interface ?

In my design, I need to access three independent DDR3 memory chips. 

I generate three DDR3 controller using MIG 7 Series 1.6. 

It seems to take about 50us time to wait until the init_calib_complete is 1 that my design can work. 

It’s a long time to wait and I can’t bear.

Could anyone tell me how to avoid the initialization process while simulating? Or how to accelerate this initial stage ?

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vsrunga
Xilinx Employee
Xilinx Employee
6,989 Views
Registered: ‎07-11-2011

Hi,

 

Unlike 6 series you cannot bypass entire calibration for 7 series.

Please check if SIM_BYPASS_INIT_CAL set to FAST and it is what all can be done for 7 series.

I hope 50us simulation time is common to assert init_calib_done.

if in case you are using ISIM/XSIM try in modelsim/questasim.

 

FurtherMIG 1.6 might be having many known issues, so I would sugget you to upgrade your tools and IPs for reliable results.

http://www.xilinx.com/support/answers/54025.html

 

Hope this helps

 

Regards,

Vanitha

 

 

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