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Observer
Observer
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Registered: ‎11-20-2017

How to build LPDDR4 PHY?

There is a fact that only the hardened Zynq PS memory controller supports LPDDR4. Xilinx does not provide any soft PHY IP for LPDDR4 at all. So I wonder how Xilinx's customers could prototype their LPDDR4 Memory Controller on Xilinx's platform? Do they have to build the PHY by themselves?

The AR#63305 (https://www.xilinx.com/support/answers/63305.html) seems to be a solution for running LPDDR4 at < 300MHz (as they said). But it is hard to follow this AR with only a few instructions in it.

Has anybody ran into this issue and have experiences on building LPDDR4 PHY?

Has anybody tried the AR#63305 successfully yet?

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Moderator
Moderator
889 Views
Registered: ‎11-28-2016

Hello @hungd ,

Nope, unfortunately there aren't any soft IPs for LPDDR4 and there are no plans for the current FPGA and future FPGA architectures. AR#63305 talks about what's possible but nothing has been extensively tested on the Xilinx side since on paper the UltraScale/UltraScale+ PHYs aren't capable of running one at a useful data rate.  From the customer support side of things I'm aware of a few customers that have tried to make their own custom LPDDR4 PHYs, the majority of which were not successful, and those that did get it running were only going at low data rates.

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Observer
Observer
778 Views
Registered: ‎11-20-2017

 

@ryana Could you please explain the folowing instruction in #AR 63305: What it means and how to do it?


Vref on the FPGA needs to be set to 0.183V as well. 

Regards,

Hung

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Moderator
Moderator
664 Views
Registered: ‎11-28-2016

Hello @hungd ,

Here you'll have to use external VREF and have the VREF pins for your LPDDR4 interface banks set to 0.183V.

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