How to change the ODT for Zynq PS LPDDR4 in ZCU111 IBIS model

[kharobangdo]

I am working on ZCU111 board & using Vivado 2019.2.

I need to generate an IBIS model for Zynq PS LPDDR4 with different ODT values to see which suits the best for my design. I followed the Xilinx PL and PS IBIS Model Decoders.

In Table 10, it gives me an example of Model Selector (MS): DWC_D5MPL4_80ODT_MS = DWC_D5MPL4_40 or DWC_D5MPL4_80ODT40

Decoding this using Table 5, it tells me that, for LPDDR4,

• DWC_D5MPL4_40: Output Impedance is 40
• DWC_D5MPL4_80ODT40: Output Impedance is 80 with Input Termination of 40
  

In Table 5, it show a small note under Output Impedance and/or Input Termination, stating that "*Output and termination impedances are not adjustable on the PS DDR controller". Is there a way to change the ODT setting for this Zynq PS LPDDR4 to generate an IBIS model?

[calebd · Accepted solution]

@kharobangdo 

The output from the IBIS models from Vivado when you target your LPDDR4 part should provide adequate ODT values per our PCB and hardware guidelines.  You can't change that value as it is fixed per our controller to the LP4 device.  This isn't a configurable option.  Changing ODT in the IBIS model would give you bad data that we can't verify and would likely cause failure if operating outside the parameters we set in UG583, UG1075, and UG1085.