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Adventurer
Adventurer
1,130 Views
Registered: ‎01-20-2017

How to choose input delays for DDR3 DQS signals

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I'm implementing a design on an KC705 development kit which incorporates the DDR3 memory interface.  I believe most of the timing constraints for the DDR3 are added to the project through use of the memory interface generator (MIG).  However, after synthesis, I run the Timing Constraints Wizard and the Input Delays page indicates that proper input delays have not been set for the two signals ddr3_sdram_dqs_p/n (please see attached image).   What is the general process for identifying the correct delay amount to use?

1. Do I need to identify the trace lengths between the DDR3 memory and the FPGA and assume a signal speed (is 15 cm / ns a reasonable speed to use?)?

2. Do I grab the datasheet for the particular memory type that is in the design and is the expected input delay specified there?

3. Or is there a Xilinx document that indicates the proper input delay to use for this development kit?

 

ddr3_sdram_dqs_input_delay_page.PNG
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Moderator
Moderator
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Registered: ‎08-21-2007

The inpue delay on DQS is not required, as the phase between DQ and DQS is adjusted during calibration after MIG IP is out of reset.

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Scholar
Scholar
1,090 Views
Registered: ‎02-01-2013

 

DQS are strobes used to clock data into the FPGA during memory reads or into the DDR chip for memory writes. There is no operational timing requirement* for the DQS signals with respect to any clock signal, so you don't need this constraint.

-Joe G.

* There is a loose, general requirement regarding the relationship between DQS signals and the DDR Clock signal, but that requirement is handled during the PCB routing of the signals between the FPGA and the memory chips.

 

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Moderator
Moderator
1,081 Views
Registered: ‎08-21-2007

The inpue delay on DQS is not required, as the phase between DQ and DQS is adjusted during calibration after MIG IP is out of reset.

-----------------------------------------------------Please don't forget to give kudos or accept as solution if information provided is helpful.---------------------------------------------------------------------

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Adventurer
Adventurer
1,070 Views
Registered: ‎01-20-2017
Thanks @kren. So I guess it's ok to identify these dqs signals as 'false paths' in the timing constraints?
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