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mabbi
Observer
Observer
1,626 Views
Registered: ‎05-04-2018

How to connect mig 7 pins for synthesis

Hi,

 

I have a Zynq ZC706 board and I created a custom AXI IP via "Tools/Create and Package new IP".

Within this IP, I need the DDR3 (SODIMM) memory.

 

Screenshot from 2018-07-11 16-28-28.png

 

I created the memory controller as described in this turoial.

Then I copied the memory model from the example project and (instantiated it 8 times) connected it to the memory controller.

 

Now the simulation nearly works.

I can write to the first six 512 bit words.

I verified it by looking at the memory[0:32767][63:0] variable of the ddr3 model.

 

The first problem: When I try to write more words, the memory controller does not assign the app_rdy to high anymore, while the ddr wires "rst_n, cke, cs_n, ras_n, cas_n, we_n" are all high:

Screenshot from 2018-07-11 16-11-04.png

 

The second problem: When I send a read signal ( cmd=1 ), mig answers with a short "ddr_r_valid = 1" (this is correct) while "ddr_r_data" is "XXXX...".

 

The third problem I have: The address bus of the mig has a width of 29 bits. How can I address the full 1GiB of the DDR3 memory?

 

 

Then I have a problem when I want to synthesize my design.

 

How do I connect all the ddr3_* ports. Do I leave them unconnected?

Since I already read from a constraints file while stepping through the mig generation GUI (as described in the tutorial), I assume Vivado already knows how to connect them?!

 

And what about the clock and reset signals?

Clock is differential, so I cannot connect it to the clock I get from the ZYNQ Processing system (S_AXI_ACLK).

 

Well, a lot of problems. I'm working on this for one week now.

Any idea to any problem would really help!

 

Thank you!

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8 Replies
rajeshkhanna
Adventurer
Adventurer
1,565 Views
Registered: ‎08-09-2013

Hi,

 

You can directly insert the ip basebuilder instead of taking through the custom new ip. or  you can instantiate the ip outside the base builder. write an simple hdl code to generate the required control for write and read access. if this works then try add the module inside the base builder through new ip.

 

The first problem: 

When I try to write more words, the memory controller does not assign the app_rdy to high anymore, while the ddr wires "rst_n, cke, cs_n, ras_n, cas_n, we_n" are all high:

 

please follow the attached info for write into ddr.

 

The second problem: When I send a read signal ( cmd=1 ), mig answers with a short "ddr_r_valid = 1" (this is correct) while "ddr_r_data" is "XXXX..."

 

for read access also there is timing cycle in the UG586, please follow.

 

The third problem I have: The address bus of the mig has a width of 29 bits. How can I address the full 1GiB of the DDR3 memory?

 

You can access the entire memory, since the wrapper compensate by increasing the number of bits. so during write and read you will get more data bits per address.

Since the pin constraints are already taken during the mig generation, you need not specify once again.

You need to mandatory ref clock to be given as per the schematics of the  design which usually is differential, map the differential clock. reset can be from the board or custom internally generated.

 

 

ddr_write.bmp
mabbi
Observer
Observer
1,560 Views
Registered: ‎05-04-2018

Hi,

 

thanks for your answer.

 

What is the base builder? Is this the block design? Unfortunately, I cannot create the MIG there because the interface then only allows me to use the AXI protocol. I'd really like to do this, since it automatically connects eveythin for me, but I assume AXI is much to slow for the DDR3 memory. (The Memory controller can read 512 bit per clock cycle, while AXI can only transer 32 bit per cycle).

 

Writing: I know the attached timing diagram and I always write directly before sending the command, so this should not be the problem.

For reading, I wasn't able to find any constraints. The datasheet says I just have to assign "cmd, addr, en" and wait for valid data.

 

Maybe I do not understand the address correctly. In the example, mutiples of 8 are used to address the 512-bit words.

Is this correct? Since I always want to read all 512 bit, I could set the last 3 bits hard to zero.

But when I write to the memory, it seems that the addresses are wrong since I access theese words:

 

Addr | Word

0        0

8        1

16      2

24      3

32      4

48      5  <= ???

64      6  <= ???

 

Thanks for your help!

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rajeshkhanna
Adventurer
Adventurer
1,555 Views
Registered: ‎08-09-2013

hi,

 

please find the screen shot. May help you.

 

Since it is an evaluation board just all the ucf details are already available so need not go through mig to generate automatically initiated when enabled through board components into base design.

ddr_base_builder.png
rajeshkhanna
Adventurer
Adventurer
1,553 Views
Registered: ‎08-09-2013

Hi,
data length provided by the ip is 512 bits and address length for the zc706 ddr3 sodimm is 27 downto 0. we need to write 512 bytes of data in each address. while reading we will get 512 bytes of data for each address we read from through the ip core.
mabbi
Observer
Observer
1,546 Views
Registered: ‎05-04-2018

I know, creating the MIG block with AXI interface is very easy. But then, I need to create a new AXI port on my IP.

I assume AXI FULL is correct, right? But I can only select a data width of 32 bit in the "Create and Package New IP" dialog. The transfer rate would result in:

32bit * 200MHz = 800MByte/s

 

while the DDR3 memory offers:

64bit * 1600MHz = 12.800MByte/s

 

and the User Interface of MIG would allow:

512bit * 200MHz = 12.800MByte/s

 

Of course there are delays, but I want to read big serial data, so I could neary reach this maximum with UI, but never with AXI.

 

Is there any mistake in my calculation?

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mabbi
Observer
Observer
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Registered: ‎05-04-2018

I just tried it out.

It was very easy. I just added the mig to the block design, ran autoconnection, and generated the bitstream.

Now I can access the DDR3 SODIMM. I wrote and read some data: working.

 

But writing and reading 128Mi addresses (means 512MiByte of data) takes about 20-35 seconds each,

so the transfer rate is about 22MB/s. Reading is even slower.

 

When I create a block on the local memory (component memory, 32bit, 1333MHz), I reach transfer rates of 350MB/s.

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mabbi
Observer
Observer
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Registered: ‎05-04-2018

Okay, sorry for the many messages, but my whole problem can now be bound to one question.

I saw that the MIG with AXI interface creates a 512 bit width data AXI port:

 

Screenshot from 2018-07-12 12-51-46.png

 

But when creating a new AXI Peripheral, I can only select 32 bit data width:

 

Screenshot from 2018-07-12 12-53-12.png

 

So how can I use the full bandwidth of the MIG7 (512 bit with 200MHz PL clock) with my own API IP?

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rajeshkhanna
Adventurer
Adventurer
1,512 Views
Registered: ‎08-09-2013

Hi,
it is already internally taken care while auto connection setting is applied. In my case i have put the ip outside the base builder. written two wrappers in hdl as per the earlier screen shot. you can see in the ila write and read data. with AXI it is simpler and easier but latency and bandwidth is as per AXI limitations. if you go through second approach HDL can be modified as per your need.