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arash9k
Adventurer
Adventurer
10,630 Views
Registered: ‎02-12-2013

How to debug "Processor is stalled at memory access."

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Hi,

 

I have a simple Microblaze block design with a MIG. And I have 2 almost identical boards with memory interfaces. The only difference between the 2 boards is that in one from the FPGA to the memory interface, the trace lengths are longer than the other one. Also in the one with longer trace lengths the DDR pins go through an additional connector mate.

 

On the board with shorter traces, when I use XMD to read a memory address in the DDR using the command "mrd 0x90000000" for example I get a numerical output which is good. But on the other board when I do a similar read I get:

 

ERROR: Cannot read from target

Processor is stalled at memory access.

 

- What could be causing this?

- How can I debug this?

- Could this be caused by the longer trace lengths? If so, is there any hope I can get this to work by making adjustments to MIG?

 

Also related to this: How would I check to see if the DDR controller has finished calibrating?

 

Any help would be much appreciated.

 

Thanks!

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yenigal
Xilinx Employee
Xilinx Employee
18,502 Views
Registered: ‎02-06-2013

Hi

 

Refer below doc for the hardware design guidelines and debug sections

 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf

Regards,

Satish

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criley
Xilinx Employee
Xilinx Employee
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Registered: ‎08-16-2007

MIG has trace length matching requirements and the additional length and connector may be causing signal integrity problems on the memory I/O.

 

I'm not sure which version of MIG, Vivado, what FPGA device, or memory type you are targeting but you can refer to the corresponding MIG User Guide and they should have all their trace length matching and memory guidelines defined there. Some of the UG's also include hardware debug sections which may prove useful. I suspect you are having calibration failures since the memory cannot be accessed.

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arash9k
Adventurer
Adventurer
10,610 Views
Registered: ‎02-12-2013

Thanks for the reply! I'm using:

 

MIG version 2.1 in IPI

Vivado version 2014.2

FPGA is xc7v2000T-flg1925 speed grade -1

Memory type is: Micron SODIMM MT16KTF51264HZ-1G6

 

Could you please point me to the UG that talks about the trace length requirements?

 

Thanks a lot!

 

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yenigal
Xilinx Employee
Xilinx Employee
18,503 Views
Registered: ‎02-06-2013

Hi

 

Refer below doc for the hardware design guidelines and debug sections

 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf

Regards,

Satish

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vsrunga
Xilinx Employee
Xilinx Employee
10,592 Views
Registered: ‎07-11-2011

Hi,

 

I would suggest to test your DDR2 chips in standalone mode so that you can isolate if the issue is with board or microblaze and MIG interface.

You can refer "Using MIG in Vivado Design Suite" from UG586 and build example design.

If in case it fails go through harddware debug guide and cross check all the steps one by one.

http://www.xilinx.com/support/answers/43879.html

 

Hope this helps

 

-Vanitha

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