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Registered: ‎11-01-2020

How to design the DDR as a DDR slave interface


In my design, I want to design a CPU DDR interface. FPGA is as the slave device which is considered as DDR chip by CPU. Can I use a MIG IP to generate the DDR interface, keep the PHY and change the upper code?

If so, how can I generate the initialization signals?

Does anybody have the related experience?

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Registered: ‎01-09-2019


You can access DDR in the PL through the MIG IP which is documented in PG150:

This has easy accessibility through the AXI interface that allows for external access to the MIG.  If your CPU is a Zynq device or a Microblaze architecture you can easily connect via the AXI interface to access DDR in this manner.  There is also a Application/User interface version that you could use to connect to a custom IP if you did not want to utilize an AXI interface (though most of our IP is AXI-based so would be best off to use that).

Alternatively, you can also create a custom controller on top of a PHY-only design, but note that this is quite difficult and there is not much/any support Xilinx can provide above what is documented in PG150.  This would be a design effort completely on your end to work from the PHY upwards.  Again, since this would be much more difficult I would suggest using the AXI interface version unless you have a specific design need that our controller cannot meet.  The PHY Only interface is described starting on page 161.




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