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wsherman@ge
Newbie
Newbie
1,250 Views
Registered: ‎10-10-2019

How to export a DDR4 timing model from a Kintex UltraScale design to be used in HyperLynx SI DDRx Wizard

I am implementing a DDR4 controller in a Kintex UltraScale FPGA using the Xilinx MIG, and I would like to run HyperLynx SI DDRx Wizard on my board design. The DDRx wizard requires a timing model for the DDR4 controller to provide min/max skew between CLK and ADDR/CMD/CTL signals, CLK to DQS, DQS to DQ, and DQS to DM, as well as setup and hold time for reads. This information should be dependent on how the DDR4 controller is implemented in the logic of the FPGA, and thus I would expect to be able to export this information (or at least view it in Vivado) somehow. Any instructions for this? Please and thanks.

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samhendr
Xilinx Employee
Xilinx Employee
1,190 Views
Registered: ‎03-14-2016

Hello, 

I have attached DDRx timing parameters for UltraScale PL DDR4 for 1866, 2133 and 2400 Mbps.

Thank you,
Sam

 

hungdang
Newbie
Newbie
1,005 Views
Registered: ‎04-28-2020

Dear Sam,

I'm using xczu7evffvc1156 part from Xilinx.

Can I use UltraScale DDR4 2400Mbps DDRx Wizard.pdf for my part number?

Thanks.
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samhendr
Xilinx Employee
Xilinx Employee
917 Views
Registered: ‎03-14-2016

Hello,

For the xczu7ev device, you will need to use the UltraScale+ timing parameters.  I have attached two models.

  • UltraScale+ PL DDRx 2400Mbps  
  • Zynq MPSoC PS DDRx 2400Mbps

Thank you,
Sam