01-27-2020 08:18 AM
I am implementing a DDR4 controller in a Kintex UltraScale FPGA using the Xilinx MIG, and I would like to run HyperLynx SI DDRx Wizard on my board design. The DDRx wizard requires a timing model for the DDR4 controller to provide min/max skew between CLK and ADDR/CMD/CTL signals, CLK to DQS, DQS to DQ, and DQS to DM, as well as setup and hold time for reads. This information should be dependent on how the DDR4 controller is implemented in the logic of the FPGA, and thus I would expect to be able to export this information (or at least view it in Vivado) somehow. Any instructions for this? Please and thanks.
05-22-2020 09:28 AM