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Adventurer
Adventurer
9,592 Views
Registered: ‎02-12-2013

How to get complete access to an 8GB memory module using MIG and Microblaze?

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Hi,

 

I'm using IPI in Vivado to create a MIG memory controller. I can successfully read/write data to my memory module. However, I'm only using 1GB of the memory module (the AXI address range is from 0x80000000 to 0xBFFFFFFF).

 

How can I get access to all the 8GB of my memory? Microblaze registers range from 0x0 to 0xFFFFFFFF and this will only give me 4GB (from which some need to be used for MDM, interrupt controller, etc).

 

Could anyone please help me find a way to use the entire 8GB?

 

Thanks.

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Xilinx Employee
Xilinx Employee
16,559 Views
Registered: ‎07-11-2011

HI,

 

If you have many pheripherals and limited addresses  I am not sure how you can have fixed address map to cover entire 8GB but if you have sufficient address range and the tool do not allow you,  please check below discussion

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Vivado-2013-3-IP-integrator-address-editor-offset-address-can/td-p/394531

 

 

Hope this helps

 

-Vanitha

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Xilinx Employee
Xilinx Employee
16,560 Views
Registered: ‎07-11-2011

HI,

 

If you have many pheripherals and limited addresses  I am not sure how you can have fixed address map to cover entire 8GB but if you have sufficient address range and the tool do not allow you,  please check below discussion

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Vivado-2013-3-IP-integrator-address-editor-offset-address-can/td-p/394531

 

 

Hope this helps

 

-Vanitha

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Adventurer
Adventurer
9,552 Views
Registered: ‎02-12-2013

Hi Vanitha,

 

Thanks very much for the link. This seems like a pormising solution for me. The only thing I am not sure about is how to increase the address space from 32 bits to 34 bits. In the forum that you references the original poster has somehow managed to use a 34 bit address space. Do you know how I can achieve this?

 

Thank!

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Xilinx Employee
Xilinx Employee
9,477 Views
Registered: ‎07-11-2011

Hi,

 

I think they might be sharing the address bus or using AXI interconnect and some othe rlogic,  you can ask the question in that thread and get their design details.

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