11-04-2020 08:10 AM
I am using the MIG DDR4 controller using User interface setting (Ref. https://www.xilinx.com/content/dam/xilinx/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf#nameddest=xDDR3DDR4DesignFlowSteps , page 122)
The interface, however, doesn't support burst count signals. Is there anyway to have that feature appears in the User interface?
11-24-2020 08:02 PM
Hi, thank for your reply.
My current design interface is based on Altera Avalon and it is much easy to convert Avalon to MIG user interface.
I also tried to use AMM Master bridge (https://www.xilinx.com/support/documentation/ip_documentation/amm_axi_bridge/v1_0/pg287-amm-axi-bridge.pdf) that converts Avalon to AXI. However, the bridge doesn't support partial/sparse byte-enables except for last beat.