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nxthuan512
Observer
Observer
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Registered: ‎06-25-2020

How to read/write burst transfer from/to DDR4 using MIG in User interface

Hi,

I am using the MIG DDR4 controller using User interface setting (Ref. https://www.xilinx.com/content/dam/xilinx/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf#nameddest=xDDR3DDR4DesignFlowSteps , page 122)

The interface, however, doesn't support burst count signals. Is there anyway to have that feature appears in the User interface?

Thanks

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lettertu
Xilinx Employee
Xilinx Employee
542 Views
Registered: ‎06-02-2017

Hi @nxthuan512 

Would you like to use AXI4 interface in your design?

Burst transaction is supported by the AXI4 interface.

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nxthuan512
Observer
Observer
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Registered: ‎06-25-2020

Hi, thank for your reply.

My current design interface is based on Altera Avalon and it is much easy to convert Avalon to MIG user interface.

I also tried to use AMM Master bridge (https://www.xilinx.com/support/documentation/ip_documentation/amm_axi_bridge/v1_0/pg287-amm-axi-bridge.pdf) that converts Avalon to AXI. However, the bridge doesn't support partial/sparse byte-enables except for last beat.

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