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alexis_jp
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Registered: ‎09-10-2019

How to reduce the LUT usage of the MIG DDR4?

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I use the Xilinx MIG DDR4 IP core in my design but the number of resources it takes is huge. Over 20k CLBs..

Is there a way to reduce those LUTs? A specific configuration? What kind of logic can I remove?

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joancab
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Registered: ‎05-11-2015

No, not the AXI width but the memory data width. In another post you say you use an x72 DIMM, so no way...

20k LUTs is a lot but for a vu9+ (1182 k LUT)  is a small bit, isn't it? 

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joancab
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Here is the resource usage for the MIG v2.2 for DDR4, one of these things to check prior to start a project:

https://www.xilinx.com/html_docs/ip_docs/pru_files/ddr4.html

Usage depends on data width and on whether you implement only the Phy or the whole controller. 

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alexis_jp
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Registered: ‎09-10-2019

The LUT usage I find seems correct for Complete_Memory_Controller. Over 20K LUTs.

My question is about a potential way of optimization.

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joancab
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I don't think so. Xilinx released the MIG IP core years ago,released a number of versions allegedly improved, I suppose they have that metric (usage) in mind but if they haven't come so far with something smaller, in my opinion is time to accept it's the way it is.

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joancab
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By the size of your MIG I guess it's a 64x. DDR4 can run at some 2.4 Gb per lane so you have a total of 153 Gb/s. Question is, is that really a must? I have seen many times how DDR is over-spec'd I don't know why, maybe a confusion between clock and data rate.

What family and P/N are you targetting?

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alexis_jp
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The target is ultrascale+ vu9p with a 512b data bus.

DDR isn't only about bandwidth/speed, it's about memory size and other requirements.

I don't think reducing the clock would change anything to the number of LUTs it uses. Nonetheless, I still can try.

If there is no other way, I'll do with it then.

Thank you for the help!

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dpaul24
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@alexis_jp ,

My question is about a potential way of optimization.

Difficult unless you know the internal arch of the MIG. Then you can mess around with this IP and see if you can reduce further logic usage. I would not waste time trying to further optimize a fully functioning complicated IP core (the philosophy of using IP cores is plug n play, so that it reduces your time to market).

A specific configuration?

yes if you use it in the native interface mode instead of AXI4 mode, the logic used would be much less.

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joancab
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No, I didn't mean reducing the clock. I meant that being DDR4 that fast you might achieve the desired data rate with an 8x or 16x architecture that would certainly reduce the area.

alexis_jp
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Registered: ‎09-10-2019

Yes, that's why I asked here first, just in case it's already known.

I gave it a shot, the native mode doesn't save much compared to AXI mode.

Thanks!

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alexis_jp
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Registered: ‎09-10-2019

@joancabThe DIMM I use is x72. (ECC)

Are you suggesting me to change the custom csv to voluntary decrease the data width? (wonder if that even works)

If you suggest me to change the AXI data width, I tried at the minimum 32b, no big changes.

Could you provide more details? I don't need the full bandwidth for my design, just the size.

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joancab
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Registered: ‎05-11-2015

No, not the AXI width but the memory data width. In another post you say you use an x72 DIMM, so no way...

20k LUTs is a lot but for a vu9+ (1182 k LUT)  is a small bit, isn't it? 

View solution in original post

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alexis_jp
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Registered: ‎09-10-2019

Well, if only hardware was that easy. The DDR's pins are located right in the middle of an already congestioned area and increased the timing failures.

Anyway, I'll try to work with it..

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