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Visitor abfontao
Visitor
2,406 Views
Registered: ‎04-09-2008

How to set up a MCB project. Help needed

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Hi everyone.

As a newby on these issues, and after having been trying it myself for a while, I've finally decided to address you guys to ask you about the very beginning of all the process.

 

I'm trying to use the MIG core (v3.8) in my SP605 to control the SDRAM included on it. As a first step, the functionality I intend is very simple: I just want to perform one 32-bit-word read or write operation (not simultaneously). I'll use PicoBlaze to send the instructions, addresses, data and control signals to the user interface.

 

The steps I follow:

 

1. I create using the Core Generator a MIG project setting up my requirements: DDR3 interface, one 32-bit bidirectional port, auto refresh enabled, etc.

The application will generate an ISE project containing all the supposedly necessary files.

2. I'd like now to include the core into a design of myself. Hence I instantiate the files created by the core generation in my top.vhd changing consequently the ucf file.

 

At this point comes the first question: how do I keep the synthesis and PAR constraints of the core project in the new one I created? Do I have to put my desing into the one core generator created or the other way round?

I've tried to find an explanation on the reference design (traffic generator) but I definitely don't understand the commands of the .bat file.

 

Despite the doubts above, I've been successful in implementing the design (maybe in an erroneous way), with many warnings that I've read relate to the use of vhdl instead of verilog.

 

The problem now comes when testing the design:

This is how i proceed in a reading operation. Please, tell me if I'm wrong at some point:

- set address to be read (last 2 bits must be 00).

- set burst length (00h in my case: only reading 1 32-bit word).

- set instruction (01h for a reading operation).

- check command FIFO status.

- When empty, set command enable (just for one command clock cycle).

- check read FIFO status.

- When not empty, read the 32-bit word data into the FPGA.

- set read enable (just for one read clock cycle) to empty the read FIFO.

- check read FIFO status.

- If empty, end.

This routine won't work. If I perform two consecutive readings of the same memory position, the result given by the SDRAM differs.

Where can be the problem? The fact of using PicoBlaze may be the problem itself? Or it's just the algorithm I implemented? (all of this supposing the implementation of the design has been correct).

 

Thanks in advance for all your help.

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Visitor abfontao
Visitor
2,519 Views
Registered: ‎04-09-2008

Re: How to set up a MCB project. Help needed

Jump to solution

Already done.

 

The key point was the zio and rzq pin location and standard.

In my design I had 2 ucf files (not very orthodox, I know). I was defining those pins in the wrong ucf file, which caused the memory to be unstable: for example, two consecutive readings of the same address would display different data.

 

SDRAM control using PicoBlaze done.

View solution in original post

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Visitor abfontao
Visitor
2,520 Views
Registered: ‎04-09-2008

Re: How to set up a MCB project. Help needed

Jump to solution

Already done.

 

The key point was the zio and rzq pin location and standard.

In my design I had 2 ucf files (not very orthodox, I know). I was defining those pins in the wrong ucf file, which caused the memory to be unstable: for example, two consecutive readings of the same address would display different data.

 

SDRAM control using PicoBlaze done.

View solution in original post

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