01-03-2019 03:57 PM
01-03-2019 09:21 PM - edited 01-03-2019 09:27 PM
You can swap them with a scalpel, some 30 gauge wire and a soldering iron.
These pins are not part of the "PL" FPGA fabric. They cannot be reprogrammed by any constraints file.
Here's something you can do though - configure your FSBL to make the Zynq use 16 bit RAM instead of 32 bit RAM. I'm reasonably sure that this means it will not drive DM and DM, so their swap becomes irrelevant. You will lose half your RAM capacity (and some speed, due to reduced bus width), but at least you can get your board working well enough to test the rest of it while you wait for your revised PCB design to be manufactured.
BTW, you might want to check chapter 10 of the Zynq 7 TRM ug585 to make sure that 16 bit mode really will work for you.
01-07-2019 09:20 AM
Thanks Allanherriman for your suggestion of configure the DDR memory to 16 bit wide in the FSBL. I will try this at some point soon. Another method I'm thinking of making a small PC board with the two pin correction and stack the DDR3 memory on it and solder the small PCB with the DDR3 memory stacked on it on my main PCB.
05-10-2019 01:08 PM
Some time ago you suggested "Here's something you can do though - configure your FSBL to make the Zynq use 16 bit RAM instead of 32 bit RAM". I went to the SDK and tried create an new FSBL project. I did not see any configuration parameteres to set the Zynq use 16 bit RAM. How would you configure FSBL to make the Zynq use 16 bit RAM?
05-14-2019 09:43 PM
@aynilian We don't use the SDK here, so I'm not sure how it is done using the SDK.
But googling for "zynq 7 16 bit DDR" gives a ton of hits. The second hit (when I did it) led to a page that contained this text:
"To emulate a single bank memory I've changed in ZYNQ7 Processing System, under DDR Configuration, the Effective DRAM Bus Width to 16 Bit. I can see that when exporting the project to the XSDK and creating a new project, the lscript.ld has half size for the ddr."
05-22-2019 02:07 PM - edited 05-22-2019 02:08 PM
I just made the Petalinux build out of the 16 bit DDR memroy width selected ZYNQ 7 (See photo attached) but in the Implemented design still shows all 32 ports active in the I/O Ports Report. I tried to boot the Petalinux build with the 16 bit DDR memory width build in my board and it did throw a Kernal Panic and hung. Even though the same build worked in the Zedboard. I have tested my board DDR memroy extensively and I know it works in 32 and 16 bit access error free. So I know the data interface is okay. One thing to try is to remove one of the memory chips in the Zedboard and see if it still boots on the Zedboard (will be a waste of a Zedboard).
I'm just wondering why the I/O report still shows 32 pins connected to the DDR?