cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
chldlrtjd
Observer
Observer
675 Views
Registered: ‎06-03-2015

I have a question about real DDR3 memory bandwidth in Kintex and Zynq.

Jump to solution

Dear Xilinx experts.

Thank you very much for your excellent best supports.

I have a question about real DDR3 memory bandwidth in Kintex and Zynq.

Our FPGA receives data from 3.125Gbps serial link (GTX).

I guess the data rate and datapath are 32 bits @ 62.5 Mhz.

I would like to store/read the data stream into/from DDR3 memory simultaneously.

Is it possible in Kintex and Zynq ?

How can I implement it?

Should I use DMA?

Thank you very much.

0 Kudos
1 Solution

Accepted Solutions
rpr
Moderator
Moderator
657 Views
Registered: ‎11-09-2017

Hi @chldlrtjd 

Are you looking for Kintex and Zynq ultrascale or 7 series? Xilinx Provides memory interface generator over Kintex and Zynq devices and also PS DDR interface over Zynq.

PG150 - UltraScale Memory Product Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

UG1085 - Zynq UltraScale+ Device Technical Reference Manual

UG585 - Zynq-7000 SoC Technical Reference Manual

Vivado provides block design, create design and you can add IPs as per your requirement and validate the design.

You can implement the design.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.

View solution in original post

0 Kudos
4 Replies
rpr
Moderator
Moderator
658 Views
Registered: ‎11-09-2017

Hi @chldlrtjd 

Are you looking for Kintex and Zynq ultrascale or 7 series? Xilinx Provides memory interface generator over Kintex and Zynq devices and also PS DDR interface over Zynq.

PG150 - UltraScale Memory Product Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

UG1085 - Zynq UltraScale+ Device Technical Reference Manual

UG585 - Zynq-7000 SoC Technical Reference Manual

Vivado provides block design, create design and you can add IPs as per your requirement and validate the design.

You can implement the design.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.

View solution in original post

0 Kudos
u4223374
Advisor
Advisor
655 Views
Registered: ‎04-26-2015

@chldlrtjd That should be easy, depending on how you configure the RAM. For a Zynq 7000, you can have 32-bit RAM at 1066MT/s = 34133Mbit/s. You never get the full bandwidth, but if you do linear reads/writes to RAM and the CPU isn't occupying too much bandwidth then getting >80% of the full bandwidth should be quite achievable.

 

The trick here will be appropriate buffering. You don't want to be writing one byte, reading one byte, writing one byte, reading one byte, etc. Much better to write 1KB, read 1KB, write 1KB, read 1KB, etc.

647 Views
Registered: ‎07-23-2019

 

DDRx memory (all of them, from DDR to DDR4) is single-access, you either read or write, never both (strictly speaking) simultaneously.

But....

As @u4223374 mentions, the best data rates are obtained when you transfer blocks, so with the proper use of buffering and DMA functions you can achieve high and (apparently) simultaneous r/w operations. Note that buffering causes latency and desynchronizes read and written data. Also note that:

read data rate + write data rate ≤ DDR data rate

chldlrtjd
Observer
Observer
569 Views
Registered: ‎06-03-2015
Dear Pratap, u4223374, archangel-lightworks

Thank you very much for your precious answer.

Ick-Sung Choi.
0 Kudos