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subbudexcel
Visitor
Visitor
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Registered: ‎05-26-2015

IBIS model of virtex 6 for DDR3 SODIMM batch simulation

we have generated the IBIS model of virtex 6 from ISE, but it still does not have ODT setting and driver strengths detail(model selector).

I understand  from the datasheet virtex 6 supports various driver strengths and ODT setting (40, 60, 120 ohm). i would request you to share ibis model which contain all the driver strength and odt setting defined (model selector).

 i have attached the ibis generated from ISE, and one more thing all the DQ and DQS line are declared as only input,

 

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gnarahar
Moderator
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Registered: ‎07-23-2015

@subbudexcel I believe this is answered in your SR filed with Xilinx 

 

Posting details for other users reference

 

  1. ODT (On Die Termination) is inside DDR memory and DCI (digital controlled impedance) is inside FPGA.
  2. The ODT setting you see in MIG Core Gen is what the controller will set on the DDR3 memory. 
  3. There is no drive strength setting for SSTL15 in Virtex 6.

You will need to edit the existing .ibs file to include [Model_Selector] to include SSTL15_DCI_I and SSTL15_DCI_O for DQ/DQS. 

 

This white paper provides more info on the Simulations for DDR3 wrt Virtex-6

 

http://www.xilinx.com/support/documentation/white_papers/wp420-DDR3-SI-PCB.pdf

- Giri
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wouter81
Visitor
Visitor
6,561 Views
Registered: ‎06-17-2015

@subbudexcel Got this issue figured out?

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gnarahar
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6,552 Views
Registered: ‎07-23-2015

@wouter81 What is the issue you are facing?

- Giri
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Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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wouter81
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Registered: ‎06-17-2015

None, with the Virtex6 at least. Was just checking because the TS's problem (adding model selectors) is something that is easy to fix manually.

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