09-28-2014 12:44 AM
Hello,
In UG471, it says, IDELAYCTRL modules exist in every I/O column in every clock region.
However, in Kintex-32T MIG DDR3-1600-64bit Design. I can only find one IDELAYCTRL instance.
as we know, DDR3-1600-64bit Design, need one io bank for ddr3 address, and two io bank for ddr3 dq.
two io bank can share one IDELAYCTRL instance?
can you help me.
sincerely,
seyior
09-29-2014 02:38 AM
Hi,
Yes it is for one bank, I just realized that you are using X64 bit interface, please check below link for the steps to find out IDELAYCTRL instances, I hope the approach remains same for 7 series
http://www.xilinx.com/support/answers/24704.htm
Regards,
Vanitha
09-28-2014 04:17 AM
Hi,
All the banks of MIG interface lies in one column and hence can share one IDELAYCTRL instance
Regards,
Vanitha
09-28-2014 06:16 AM
two io bank can share one IDELAYCTRL instance?
It is true that there is one IDELAYCTRL per bank, and the IDELAY/ODELAY cells in that bank use that IDELAYCTRL.
However, the tools will replicate instantiated IDELAYCTRL cells. The IDELAYCTRL cell takes two inputs (a clock and a reset) and generates one output (locked, that is usually ignored). These signals can be routed anywhere on the die (assuming the clock comes from a BUFG), therefore, they can be connected to the IDELAYCTRL in any bank. When the tool sees a bank that has IDELAY/ODELAY cells instantated and there is one (and only one) IDELAYCTRL instantated in the design, it will connect the clock and reset signal to the IDELAYCTRL cells in each bank that has IDELAY/ODELAY (and AND the locked signals together, I think).
If you need to use different clock, reset and locked signals, you group IDELAY/ODELAY and IDELAYCTRL cells using the property IODELAYGROUP - this tell the tools which IDELAYCTRL needs to be replicated in a given bank. You cannot have two different IODELAYGROUP groups in the same bank (since there is only one IDELAYCTRL).
Avrum
09-28-2014 06:44 AM
Hi,
Just to add on to the discussion, you can refer to http://www.xilinx.com/support/answers/39966.htm
Thanks,
Deepika.
09-28-2014 06:57 PM
Dear Vanitha, Avrum, Deepika.
Thanks for your kindly help!
really, i can find only one IDELAYCTRL instance in fpgaeditor and planahead.
where can i find " IDELAYCTRL share rule" in xilinx document?
sincerely
seyior.
09-28-2014 09:46 PM
Hi,
Below figure shows IDELAYCTRL locations in 7 series device, for your specific configuration it is possible that you might have one IDELAYCTRL
Regards,
Vanitha
09-29-2014 02:24 AM
Dear Vanitha,
In ug472_7Series_Clocking.pdf,
it says one clock region is for one i/o bank.
page 11
----------------
A clock region includes all synchronous elements (for instance: CLB, I/O, serial
transceivers, DSP, block RAM, CMT) in an area spanning 50 CLBs and one I/O bank
(50 I/Os), with a horizontal clock row (HROW) in its center.
----------------
so, one IDELAYCTRL instance is for one i/o bankd?
sincerely,
seyior
09-29-2014 02:38 AM
Hi,
Yes it is for one bank, I just realized that you are using X64 bit interface, please check below link for the steps to find out IDELAYCTRL instances, I hope the approach remains same for 7 series
http://www.xilinx.com/support/answers/24704.htm
Regards,
Vanitha
09-29-2014 07:14 PM
Dear Vanitha,
thanks your help very much!.
I use ISE's "Generate Post-Place & Roue Sikmulation Model".
in the generated "xx_timesim.v" file, i can find 2 idelayctrl instances in MIG Module.
so, one idelayctrl instance for on i/o bank(region) is true.
sincerely,
seyior