cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Participant
Participant
819 Views
Registered: ‎11-11-2016

ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

Hello,

We are trying to debug the example_top.v design for a 4.2 version MIG for DDR3 SDRAM targeting a XC7K325T Kintex-7 FPGA. Opening the synthesized design, the dbg_hub clock pin is connected to the ui_clk of the MIG, and opening the implemented design, the VIO and ILA cores are displayed on the "Device" view.

Generating the probes file (write_debug_probes probes.ltx on the TCL console) and programming the device through Vivado Hardware Manager, nevertheless the following messages appear:

program_hw_devices [get_hw_devices xc7k325t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1836.281 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'CHIPSCOPE_INST.u_vio_twm_ddrx' at location 'uuid_5EED9D980522516D9A6501A91A4F4198' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'CHIPSCOPE_INST.u_ila_ddr3_axi' at location 'uuid_B5362B1FF63254438E3C9B950CA79C47' from probes file, since it cannot be found on the programmed device.

Both project and hardware manager are version 2019.2, working on a Windows 10 Pro machine.

Thanks in advance, best regards.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Participant
Participant
396 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

travisc, bethf,

issue is solved: signals are now triggerable from ILAs. MIG-associated clock constraints were not automatically included in the example design, so I had to import them manually.

Thanks for helping! Regards.

View solution in original post

14 Replies
Highlighted
Xilinx Employee
Xilinx Employee
730 Views
Registered: ‎11-10-2008

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

Hello, when using ILA/VIO, you must use a free running clock.  An MMCM output cannot be used.  This Answer Record is for MIG UltraScale but the same idea can be applied to MIG 7-Series. 

https://www.xilinx.com/support/answers/66054.html

Thanks.

0 Kudos
Highlighted
Participant
Participant
724 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

Hello bethf,

thanks for your reply! Having on the board a single oscillator driving the sys_clk_p/n signals being routed into the MIG instance, does this mean should I instantiate a IBUFDS driver as well for feeding the ILA logic?

Is this allowed?


Thanks in advance!

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
718 Views
Registered: ‎11-10-2008

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

You will not use another IBUFDS.  Rather, use the clock output from your existing buffer structure (ie, BUFG).

0 Kudos
Highlighted
Participant
Participant
664 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

bethf,

thanks again! Through the MIG GUI, I selected "no buffer" on the system clock option, and "use system clock" for the reference clock. In the "example_top.v" file, I modified the sys_clk_i input with the differential sys_clk_p and sys_clk_n ports, and subsequently declared a sys_clk signal as output of an IBUFDS and input of a BUFG as follows:


IBUFDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("FALSE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("DIFF_SSTL15") // Specify the input I/O standard
) IBUFDS_inst (
.O(sys_clk), // Buffer output
.I(sys_clk_p), // Diff_p buffer input (connect directly to top-level port)
.IB(sys_clk_n) // Diff_n buffer input (connect directly to top-level port)
);

BUFG BUFG_inst (
.O(sys_clk_i), // 1-bit output: Clock output
.I(sys_clk) // 1-bit input: Clock input
);

The sys_clk_i signal is currently used as input for the MIG and feeds the ILA and VIO logic. The related processes updating the ILA and VIO signals are now updated on sys_clk_i instead of the ui_clk signal derived from the MIG.

Would you please confirm this is the strategy to follow? Thanks in advance!

Best regards.

0 Kudos
Highlighted
Participant
Participant
649 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

bethf,

by implementing the design as previously described, ILA and VIO are correctly recognized in the Vivado Hardware Manager. Nevertheless, the linked signals for debugging are now not present in the scope.

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
638 Views
Registered: ‎11-10-2008

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

Great to hear the initial issue is resolved.  Have you tried using the MIG example design with the Debug signals enabled?  This will give you a working example of ILA and VIO connection with the MIG IP.  To generate, create the MIG IP, enable the "Debug Signals for Memory Controller" option, after allowing the IP to generate output products and synthesize, right click and select "Open IP Example Design".  This should get you running.

Thanks,

-Beth

0 Kudos
Highlighted
Participant
Participant
614 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

beth,

thanks for helping! I was already running the example design of the MIG as you suggested. Moving forward, the HW manager now also recognizes the signals connected in the ILAs and VIOs as follows.

program_hw_devices [get_hw_devices xc7k325t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1839.688 ; gain = 0.086
refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 ILA core(s).
INFO: [Labtools 27-2302] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 VIO core(s).
INFO: [Labtools 27-1967] Uploading output probe values from VIO core [hw_vio_1], for hw_probes which did not have this property set
refresh_hw_device: Time (s): cpu = 00:00:15 ; elapsed = 00:00:07 . Memory (MB): peak = 1860.500 ; gain = 20.813
display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7k325t_0] -filter {CELL_NAME=~"CHIPSCOPE_INST.u_ila_ddr3_axi"}]]

 

However, when trying to set up a trigger to display the waveform, the following error message occurs:

run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7k325t_0] -filter {CELL_NAME=~"CHIPSCOPE_INST.u_ila_ddr3_axi"}]
ERROR: [Labtools 27-3428] Ila core [hw_ila_1] clock has stopped. Unable to arm ILA core.


Opening the synthesized design, ILA and VIO are present and connected to the free running clock, although a warning window pops up, declaring "No debug core were found". How should I proceed?

Thanks in advance, best regards.

0 Kudos
Highlighted
Participant
Participant
584 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

beth,

within the example_top.v file, I connected the ui_clk signal coming as output from the MIG (which feeds the ILA and VIO logic) to an output pin and then to a probe with an oscilloscope. The result  is a 0.3mV signal. No clock activity is detected.

I guess this is the reason why the HW manager states the "clock has stopped" error. How is it supposed to work?


Thanks again, regards.

0 Kudos
Highlighted
Participant
Participant
570 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

beth,

sorry for multiple posting, I just want to keep you updated so I might reach a solution with fewer interations. Currently, I modified the processes in the  example_top.v file by substituting the MIG-derived clock with the BUFG output that you suggested. So, at this moment, the processes look like this:

always @(posedge sys_clk_i) begin

instead of

always @(posedge clk) begin

 

With these modifications, ILAs and VIO are recognized in the HW manager, and triggerable, as the signals are updated on the rising edge of the free running clock. Nevertheless, all values are kept at 0 with no updates.

I have noticed that for the Ultrascale family solution, a clock divider macro was instantiated along with the clock buffer. Is it necessary for the 7-series family as well? Is that primitive allowed for this family?

Thanks in advance, best regards.

Capture.PNG
0 Kudos
Highlighted
Moderator
Moderator
559 Views
Registered: ‎10-19-2011

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

What is your clock frequency of the ILA? If its equal to or slower than what you are capturing that would be a problem. Did you just modify the clock manualy, or did you use the ILA wizard to reconfigure the whole ip? You may want to completly remove the existing ILA and then go in through the ILA wizard and set it up directly. That way the clocking is handled internaly, and it should pick the appropriate free running clock path.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Highlighted
Participant
Participant
475 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

travisc,

thanks for replying! The current ILA clock frequency is 200MHz. As I was told by bethf the ILA has to be fed by a free running clock, I manually modified the code.

If I was to remove the ILA, should I proceed through the "Set Up Debug" in the Synthesized Design or should I redefine a new ILA IP? I previously tried the solution you are suggesting, however the ILA IP wizard did not allow for configuring a 144-port IP as required by one of the ILAs in the example design.

Thanks in advance, best regards.

0 Kudos
Highlighted
Participant
Participant
411 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

travisc,

concerning the clock frequency of the clock buffer feeding the ILA, I simulated the "example_top" design and checked the MIG-generated clock frequency: it stands at 200MHz, which is equal to the system input clock frequency.

Currently, the differential clock signal is entering into an IBUFDS and successively into a BUFG for feeding the ILA with a free running clock. Processes are also updated on this clock. Therefore, logically, no difference stands between the two designs. In fact, simulation provide an equivalent test result.

Nevertheless, probed signals when opened in the Vivado Hardware Manager in the ILA are kept at a zero constant value despite the equal clock frequency. How should I proceed?

Thanks in advance. Best regards.

0 Kudos
Highlighted
Participant
Participant
410 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

travisc,

sorry for multiple posting. Just to keep you updated, the issue was concerning the management of the reset signal. Nevertheless, now if triggering the ILA, the following error message appears in the HW manager:

ERROR: [Labtools 27-3312] Data read from hw_ila [hw_ila_1] is corrupted. Unable to upload waveform.

I keep digging. If any suggestion arises, please reply.

Thanks in advance.

0 Kudos
Highlighted
Participant
Participant
397 Views
Registered: ‎11-11-2016

Re: ILA and VIO dropped in Hardware Manager for MIG v4.2

Jump to solution

travisc, bethf,

issue is solved: signals are now triggerable from ILAs. MIG-associated clock constraints were not automatically included in the example design, so I had to import them manually.

Thanks for helping! Regards.

View solution in original post